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Mon, 11 Nov 2024 08:45:38 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AB8jb2B002385 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 11 Nov 2024 08:45:37 GMT Received: from [10.216.36.177] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 11 Nov 2024 00:45:33 -0800 Message-ID: Date: Mon, 11 Nov 2024 14:15:15 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] arm64: dts: qcom: qcs615: Add QUPv3 configuration To: Krzysztof Kozlowski , , , , , , , , , CC: , References: <20241028112049.30734-1-quic_vdadhani@quicinc.com> <50a0a56d-55ce-4b59-a004-b8418309eb92@kernel.org> Content-Language: en-US From: Viken Dadhaniya In-Reply-To: <50a0a56d-55ce-4b59-a004-b8418309eb92@kernel.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: DHNyrnKJ565CxYEQtZDiOfEof6tKzNMI X-Proofpoint-ORIG-GUID: DHNyrnKJ565CxYEQtZDiOfEof6tKzNMI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 malwarescore=0 mlxlogscore=999 spamscore=0 impostorscore=0 adultscore=0 phishscore=0 suspectscore=0 clxscore=1015 bulkscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411110073 On 10/28/2024 5:03 PM, Krzysztof Kozlowski wrote: > On 28/10/2024 12:20, Viken Dadhaniya wrote: >> Add DT support for QUPv3 Serial Engines. >> >> Co-developed-by: Mukesh Kumar Savaliya >> Signed-off-by: Mukesh Kumar Savaliya >> Signed-off-by: Viken Dadhaniya >> --- >> >> Build Dependencies: >> >> Base: >> https://lore.kernel.org/linux-devicetree/20240926-add_initial_support_for_qcs615-v3-5-e37617e91c62@quicinc.com/ >> https://lore.kernel.org/linux-devicetree/20240926-add_initial_support_for_qcs615-v3-6-e37617e91c62@quicinc.com/ >> >> Clock: https://lore.kernel.org/linux-devicetree/20240920-qcs615-clock-driver-v2-3-2f6de44eb2aa@quicinc.com/ >> ICC: https://lore.kernel.org/linux-devicetree/20240924143958.25-2-quic_rlaggysh@quicinc.com/ >> Apps SMMU: https://lore.kernel.org/all/20241011063112.19087-1-quic_qqzhou@quicinc.com/ >> >> v1 -> v2: >> >> - Add opp-shared property. >> - Use QCOM_ICC_TAG_ALWAYS flag in interconnect property. >> >> v1 Link: https://lore.kernel.org/all/20241011103346.22925-1-quic_vdadhani@quicinc.com/ >> --- >> arch/arm64/boot/dts/qcom/qcs615.dtsi | 642 ++++++++++++++++++++++++++- >> 1 file changed, 638 insertions(+), 4 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi >> index 865ead601f85..1d1cdf6f9a74 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi >> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi >> @@ -5,6 +5,7 @@ >> >> #include >> #include >> +#include >> #include >> #include >> #include >> @@ -17,6 +18,21 @@ >> #address-cells = <2>; >> #size-cells = <2>; >> >> + aliases { >> + i2c1 = &i2c1; >> + i2c2 = &i2c2; >> + i2c3 = &i2c3; >> + i2c4 = &i2c4; >> + i2c5 = &i2c5; >> + i2c6 = &i2c6; >> + i2c7 = &i2c7; >> + spi2 = &spi2; >> + spi4 = &spi4; >> + spi6 = &spi6; >> + spi7 = &spi7; >> + serial0 = &uart0; > > Comments from v1 apply. Updated in v3. > >> + }; >> + >> cpus { >> #address-cells = <2>; >> #size-cells = <0>; >> @@ -296,6 +312,26 @@ >> qcom,bcm-voters = <&apps_bcm_voter>; >> }; >> >> + qup_opp_table: opp-table-qup { >> + compatible = "operating-points-v2"; >> + opp-shared; >> + >> + opp-75000000 { >> + opp-hz = /bits/ 64 <75000000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-100000000 { >> + opp-hz = /bits/ 64 <100000000>; >> + required-opps = <&rpmhpd_opp_svs>; >> + }; >> + >> + opp-128000000 { >> + opp-hz = /bits/ 64 <128000000>; >> + required-opps = <&rpmhpd_opp_nom>; >> + }; >> + }; >> + >> psci { >> compatible = "arm,psci-1.0"; >> method = "smc"; >> @@ -392,6 +428,24 @@ >> #size-cells = <1>; >> }; >> >> + gpi_dma0: qcom,gpi-dma@800000 { > > Nope. Don't post downstream code. Sure. updated in v3. > > Best regards, > Krzysztof >