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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b97f17410aesm185250466b.62.2026.03.18.04.18.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 18 Mar 2026 04:18:12 -0700 (PDT) Message-ID: Date: Wed, 18 Mar 2026 12:18:09 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/3] arm64: dts: qcom: Introduce Eliza Soc base dtsi To: Abel Vesa , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski References: <20260318-eliza-base-dt-v3-0-8a50bd2201ed@oss.qualcomm.com> <20260318-eliza-base-dt-v3-2-8a50bd2201ed@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260318-eliza-base-dt-v3-2-8a50bd2201ed@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: YHxaNVkR5ram0mDVrR9rJIN-6l7zu684 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE4MDA5NSBTYWx0ZWRfX7BqHXdVUQJra SsCtJoDD0bJ3BdjgIv2m6Ulmle6C6H9FJteXyEzOqqpccE/wz6sPfpmdbwrtBpnqBWFpbnNORO4 1XuVmwqrb4xPDPuvYzc9mFgtJtI4a0DZSClfZZxjPEOmKeuVxrZAj1FsOwh9mF84wTOmAxdy48X Egy5IFF2vouWS8VjJjwLhD2SoyXqY8FjwRG7rc7RMNq4ijyLSJrj24MgPT1oGY9ukN1YmhHzzsc tG6Ndw3PwWMaIsI9s50rY0lppF0YkBLOmfK2O/Skk3HUTh/knr7ed7YendpxiTZ3fAq5s2icnCH p/lVluznyFI/afy0fVvabhAZjobBoL0uGfdB2Z7R0GUJyjcJTXpyhzij4zUhJMS0kenveHEV7dB iFysM96Rbpfaz+sjMxc1j/IMZZfZbg9oS/SBwmWhCPJMJXVPZUQCLDGvu8LS5wrauVzR6825jKR iwSGiSHjknuAZoPQlzQ== X-Proofpoint-GUID: YHxaNVkR5ram0mDVrR9rJIN-6l7zu684 X-Authority-Analysis: v=2.4 cv=PtCergM3 c=1 sm=1 tr=0 ts=69ba89f6 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=2ZscZiC02MhLG_3MCHcA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-18_01,2026-03-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 lowpriorityscore=0 malwarescore=0 spamscore=0 adultscore=0 suspectscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603180095 On 3/18/26 11:19 AM, Abel Vesa wrote: > Introduce the initial support for the Qualcomm Eliza SoC. It comes in > different flavors. There is SM7750 for mobiles and then QC7790S/M for IoT. > Describe the common parts under a common dtsi. > > The initial submission enables support for: > - CPU nodes with cpufreq and cpuidle support > - Global Clock Controller (GCC) > - Resource State Coordinator (RSC) with clock controller & genpd provider > - Interrupt controller > - Power Domain Controller (PDC) > - Vendor specific SMMU > - SPMI bus arbiter > - Top Control and Status Register (TCSR) > - Top Level Mode Multiplexer (TLMM) > - Debug UART > - Reserved memory nodes > - Interconnect providers > - System timer > - UFS > > Reviewed-by: Dmitry Baryshkov > Co-developed-by: Krzysztof Kozlowski > Signed-off-by: Krzysztof Kozlowski > Signed-off-by: Abel Vesa > --- [...] > + gcc: clock-controller@100000 { > + compatible = "qcom,eliza-gcc"; > + reg = <0x0 0x00100000 0x0 0x1f4200>; > + > + clocks = <&bi_tcxo_div2>, > + <&sleep_clk>, > + <0>, > + <0>, > + <&ufs_mem_phy 0>, > + <&ufs_mem_phy 1>, > + <&ufs_mem_phy 2>, > + <0>; power-domains = <&rpmhpd RPMHPD_CX>; [...] > + clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, > + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; please align the '<'s [...] > + ice: crypto@1d88000 { > + compatible = "qcom,eliza-inline-crypto-engine", > + "qcom,inline-crypto-engine"; > + reg = <0x0 0x01d88000 0x0 0x18000>; > + > + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; I believe you will be affected by the change (?) https://lore.kernel.org/all/20260318-precious-qualified-oryx-ef619f@quoll/ [...] > + spmi: arbiter@c400000 { > + compatible = "qcom,eliza-spmi-pmic-arb", > + "qcom,x1e80100-spmi-pmic-arb"; > + reg = <0 0x0c400000 0 0x3000>, > + <0 0x0c500000 0 0x400000>, > + <0 0x0c440000 0 0x80000>; > + reg-names = "core", "chnls", "obsrvr"; 0x0, one a line please (also below) Konrad