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Peter Anvin" , Petr Tesarik , Ravi Bangoria , Ananth Narayan , Sandipan Das Subject: [PATCH 1/3] perf/x86: Add x86_pmu::print_debug Date: Thu, 6 Aug 2026 15:33:26 +0530 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb10.amd.com (10.181.42.219) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CEB:EE_|SA0PR12MB7461:EE_ X-MS-Office365-Filtering-Correlation-Id: 615ca743-71af-46f2-0605-08def3a3c2fb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|36860700016|376014|7416014|82310400026|1800799024|6133799003|10067099003|56012099006|11063799006|18002099003|22082099003|3023799007; X-Microsoft-Antispam-Message-Info: 0uLGBZzmvsXlN3durF93oSyy/NqcKaEvGbqFxD6K82fwvo6pdnLn5Q1H+xHtu6/naORkfSxJ0WAM6MyQOKBLjbEi3RhX6B1WCrDOx7va1pCPe1JMtxDP7Rl+GaAIwWL+H12ZjFQ4isrlTYZykQzO6F8ZyF0O4awv3796aHhk2UU9/jibxThYXT0yGWc5jEXkyibBiKPWX/6sXmjiRpRAbK/msd8zEWXrsnb/4y2ayZ/950b+E2CZLxeYslEwxDbwrLfSE6ULulDNNFAMfHkHR2gbiaaB7ZH/nP4LfMSw+QxWmsjT8LdnHxnhQ+oGBc41DaZQ/0rx7PRN+dPCWbEKKof+ZE+YzdTNJ4syVNhM7WGgCnRYfqUh2+86U555hhcWQrQ2Grj4iJtHmM/XGDPHJeHqbcNoWGAyhq6qyjUT1KI/6OqdYwoQkQiqc7Zfm3NMmWzhHvrZOKp4velcYvPFbUijtfB2oJqTw6QNwMghyMzAiP812I1SrnHwSmeZm3hg2ecnPnNQ6Zm309JvjY16KM9cWnIt5dk4V/bgzqi0HbrHUfUnFN+wbVgfAIOqeVqUYs0ATrwticGqFSmjllnCFyDPWs8HA2xLQUA7kCKQcFG37Nz1Bz+1D4o/3qQE04gvLph+dPd109pJWTWPfpPwsa+31Z6iR9bR+mvnAAS3T3vMT+oUxnWPUg/FVQetCeib X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(23010399003)(36860700016)(376014)(7416014)(82310400026)(1800799024)(6133799003)(10067099003)(56012099006)(11063799006)(18002099003)(22082099003)(3023799007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: j+G58DiFGWxmrIbFHgnyrL5aVaO/HRRqbivNUWSU4NOZxjR4ESQ2ZDhRmmn2/vSs/98AayoTzm3EiAVcemSxhVPY8mU2GK6WXmxfidIcLHW6WUOg948cvtmCYeJ8Nkwaqpzr3/ilJGAYVvcwZxLjBjmrZS64bDaX2lFxscqBNnWYp1YXKunDQ4TWKV8lk7IMpwVYbAs9xRenzB4O88S2LeQrez+h2lC3zwzS5cEhpAApYDYkHKr+8BRczJ1FDrfa9SWXrpplaDxE7EvC/G2NCn1hkOsVQk4NBgu5zOPs758/27YNMKMozsbquvTo2ftOGORf85OFDcRIZ/lPTHC56qDa9rVS231LddnXWwYQmu74Ir/tFxB+VGW5Pm9NUdZYCzRvC341pymiGhMl7YxW1aGy3s15BcV15zycAV/c1kxQZ+LKCBccs1BSznDNT1dr X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2026 10:16:20.8541 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 615ca743-71af-46f2-0605-08def3a3c2fb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB7461 perf_event_print_debug() dumps the global control and status MSRs whenever x86_pmu.version >= 2, reading registers that exist only on Intel-compatible PMUs. This is not safe since x86_pmu.version is not Intel-specific and is now set by other vendors whose global registers use different addresses. As a first step, split perf_event_print_debug() in two. The register dump moves into a new common helper, x86_pmu_print_debug(), leaving perf_event_print_debug() to handle the preamble and dispatch to an optional x86_pmu::print_debug method. This lets each vendor-specific PMU dump its own global state before chaining into the common helper. PMUs that do not implement the method, such as those with x86_pmu.version < 2, get the common helper alone. No functional change intended. Signed-off-by: Sandipan Das --- arch/x86/events/core.c | 29 ++++++++++++++++++++++------- arch/x86/events/perf_event.h | 4 ++++ 2 files changed, 26 insertions(+), 7 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index af0b67ffb43d..17dc53a62378 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -1557,7 +1557,7 @@ static void x86_pmu_start(struct perf_event *event, int flags) perf_event_update_userpage(event); } -void perf_event_print_debug(void) +void x86_pmu_print_debug(int cpu) { u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; unsigned long *cntr_mask, *fixed_cntr_mask; @@ -1566,17 +1566,11 @@ void perf_event_print_debug(void) u64 pebs, debugctl; int cpu, idx; - guard(irqsave)(); - - cpu = smp_processor_id(); cpuc = &per_cpu(cpu_hw_events, cpu); cntr_mask = hybrid(cpuc->pmu, cntr_mask); fixed_cntr_mask = hybrid(cpuc->pmu, fixed_cntr_mask); pebs_constraints = hybrid(cpuc->pmu, pebs_constraints); - if (!*(u64 *)cntr_mask) - return; - if (x86_pmu.version >= 2) { rdmsrq(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, status); @@ -1622,6 +1616,27 @@ void perf_event_print_debug(void) } } +void perf_event_print_debug(void) +{ + struct cpu_hw_events *cpuc; + unsigned long *cntr_mask; + int cpu; + + guard(irqsave)(); + + cpu = smp_processor_id(); + cpuc = &per_cpu(cpu_hw_events, cpu); + cntr_mask = hybrid(cpuc->pmu, cntr_mask); + + if (!*(u64 *)cntr_mask) + return; + + if (x86_pmu.print_debug) + x86_pmu.print_debug(cpu); + else + x86_pmu_print_debug(cpu); +} + void x86_pmu_stop(struct perf_event *event, int flags) { struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index a8afea8d38f0..465bf513bb82 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -1052,6 +1052,8 @@ struct x86_pmu { int num_hybrid_pmus; struct x86_hybrid_pmu *hybrid_pmu; enum intel_cpu_type (*get_hybrid_cpu_type) (void); + + void (*print_debug)(int cpu); }; struct x86_perf_task_context_opt { @@ -1316,6 +1318,8 @@ int x86_pmu_handle_irq(struct pt_regs *regs); void x86_pmu_show_pmu_cap(struct pmu *pmu); +void x86_pmu_print_debug(int cpu); + static inline int x86_pmu_num_counters(struct pmu *pmu) { return hweight64(hybrid(pmu, cntr_mask64)); -- 2.53.0