From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 17E4C23817E for ; Mon, 1 Jun 2026 05:36:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780292191; cv=none; b=soIp0Xa62iZSrla49LWuHaUf5Kt5Y5DIa+yqx7aOC7muV0Tb+COksQMpihluCbgtWCaDgHNM3K9SuBegCs5ZYyy7myjAklvIcv45vl3nCEfFxcnjaIetCj2PStCQXoJpX2ZGRjeH7WaRCJlR5bOLWcg70+Xx1iDVUkZ1IvNCdTo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780292191; c=relaxed/simple; bh=BXihrI+kDpZcwsjIhEFPnSR9hYiTEZguWIRQRr0syf4=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=Pp5THVlbB7k0RPk4yfulCtjZp4wM0sB8YpZx9Nj8kOvNgAauKQGA7+ySINNMm5T1K26+zSrBd1BmQEcmy19JTIYCcfXk9suwKl8FBpW/+NmUyL7hzzxVmdimLY22qihZ2ubo+PUFUidJWeDAKhPZOsgxYRIOFWDu7H2AVT+y75E= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=vm2kSx94; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="vm2kSx94" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 723D11E8D; Sun, 31 May 2026 22:36:24 -0700 (PDT) Received: from [10.164.18.45] (unknown [10.164.18.45]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 644843F905; Sun, 31 May 2026 22:36:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1780292189; bh=BXihrI+kDpZcwsjIhEFPnSR9hYiTEZguWIRQRr0syf4=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=vm2kSx94I5qkogPVURWrrhH7aXHNfLmUGrxjiD+wnWosJeMfjbh5y2H7ia0qhyyQG ugqsgzAcfZSIg2Dw6IILnixHWf73Cv9uOSh+8NxrMK4tlJxUtvIMoprfHWx+JwX8Fr iXiG6LVFDVIPWd/sjZBPtJitP/i+ldzWRllI02oY= Message-ID: Date: Mon, 1 Jun 2026 11:06:22 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC V2 13/14] arm64/mm: Add an abstraction level for tlbi_op To: Linu Cherian , Ryan Roberts Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Mark Rutland , Lorenzo Stoakes , Andrew Morton , David Hildenbrand , Mike Rapoport , Usama Arif , linux-kernel@vger.kernel.org, linux-mm@kvack.org References: <20260513044547.4128549-1-anshuman.khandual@arm.com> <20260513044547.4128549-14-anshuman.khandual@arm.com> <37917d56-ae26-4789-ac4c-15f8ee12398b@arm.com> Content-Language: en-US From: Anshuman Khandual In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 29/05/26 9:32 AM, Linu Cherian wrote: > Hi Ryan, > > On Wed, May 27, 2026 at 03:50:10PM +0100, Ryan Roberts wrote: >> On 13/05/2026 05:45, Anshuman Khandual wrote: >>> From: Linu Cherian >>> >>> With FEAT_D128, a new instruction aka TLBIP is being introduced for the TLB >>> range operations which has an argument size of 128 bit. >> >> nit: TLB range operations -> TLBI-by-range operations ? > > Ack. > >> >>> >>> Add an abstraction level to void (*tlbi_op)(u64 arg) helpers to support the >>> D128 variations when applicable. >>> >>> No functional changes are introduced with this patch. >>> >>> Signed-off-by: Linu Cherian >>> Signed-off-by: Anshuman Khandual >>> --- >>> arch/arm64/include/asm/tlbflush.h | 70 ++++++++++++++++--------------- >>> 1 file changed, 37 insertions(+), 33 deletions(-) >>> >>> diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h >>> index c0bf5b398041..361d74ef8016 100644 >>> --- a/arch/arm64/include/asm/tlbflush.h >>> +++ b/arch/arm64/include/asm/tlbflush.h >>> @@ -162,49 +162,53 @@ static inline void sme_dvmsync_batch(struct arch_tlbflush_unmap_batch *batch) >>> >>> #define TLBI_TTL_UNKNOWN INT_MAX >>> >>> -typedef void (*tlbi_op)(u64 arg); >>> +typedef u64 tlbi_args_t; >> >> nit: tlbi_args_t -> tlbi_arg_t ? > > Ack. Accommodated both the changes.