Re: [PATCH 1/7] EDAC/amd64: Remove amd64_pvt::ext_nbcfg

[Yazen Ghannam <yazen.ghannam@amd.com>]

On 2/13/2024 6:20 AM, Jiri Slaby (SUSE) wrote:
> Commit cfe40fdb4a46 (amd64_edac: add driver header) added amd64_pvt
> struct with ext_nbcfg in it. But noone used that member since then.
> 
> Therefore, remove it.
> 
> Found by https://github.com/jirislaby/clang-struct.
> 
> Signed-off-by: Jiri Slaby (SUSE) <jirislaby@kernel.org>
> Cc: Yazen Ghannam <yazen.ghannam@amd.com>
> Cc: Borislav Petkov <bp@alien8.de>
> Cc: Tony Luck <tony.luck@intel.com>
> Cc: James Morse <james.morse@arm.com>
> Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
> Cc: Robert Richter <rric@kernel.org>
> Cc: linux-edac@vger.kernel.org
> ---
>   drivers/edac/amd64_edac.h | 1 -
>   1 file changed, 1 deletion(-)
> 
> diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
> index 1665f7932bac..b879b12971e7 100644
> --- a/drivers/edac/amd64_edac.h
> +++ b/drivers/edac/amd64_edac.h
> @@ -345,7 +345,6 @@ struct amd64_pvt {
>   	u32 dchr1;		/* DRAM Configuration High DCT1 reg */
>   	u32 nbcap;		/* North Bridge Capabilities */
>   	u32 nbcfg;		/* F10 North Bridge Configuration */
> -	u32 ext_nbcfg;		/* Extended F10 North Bridge Configuration */
>   	u32 dhar;		/* DRAM Hoist reg */
>   	u32 dbam0;		/* DRAM Base Address Mapping reg for DCT0 */
>   	u32 dbam1;		/* DRAM Base Address Mapping reg for DCT1 */

This field likely was intended to be used with the EXT_NB_MCA_CFG definition.
But I agree it's not used and can be removed.

Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com>

Thanks,
Yazen