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Sun, 28 Sep 2025 20:57:48 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHuArBOJSGdH2d51k037g9fbFwwwtZi2aIpgGp3j1sTG3Gq9TQVKDuopvTuXrBfvMWjx4Po8Q== X-Received: by 2002:a17:90b:314e:b0:32e:c6b6:956b with SMTP id 98e67ed59e1d1-3342a2702ebmr15297792a91.4.1759118267758; Sun, 28 Sep 2025 20:57:47 -0700 (PDT) Received: from [192.168.0.195] ([49.204.31.98]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b57c55be61bsm9939207a12.48.2025.09.28.20.57.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 28 Sep 2025 20:57:47 -0700 (PDT) Message-ID: Date: Mon, 29 Sep 2025 09:27:43 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 22/24] arm64: dts: qcom: glymur: Add display clock controller device To: Krzysztof Kozlowski , Pankaj Patil Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250925-v3_glymur_introduction-v1-0-24b601bbecc0@oss.qualcomm.com> <20250925-v3_glymur_introduction-v1-22-24b601bbecc0@oss.qualcomm.com> Content-Language: en-US From: Taniya Das In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: h1plgaZ572UVbMH9sALj0XEFOuDgw3BA X-Proofpoint-ORIG-GUID: h1plgaZ572UVbMH9sALj0XEFOuDgw3BA X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTI3MDA0MyBTYWx0ZWRfX6h3cUCnt0gH4 TsQMrwXYyt+mIqV4Q7+Q+TO30b9PbKRKYaRs0oBypItnQNNnNsPUI73Lq0UDOjziwngvY3tFbUt 2K6IaG9mPvq692j/8ZkxpQvJB/DGgZ2V2DIu7BqwjDWwGZQLENpNazUa6+ld4R2onlZil2iDj/9 ujMMit41C4VAaRI40y52nHDedH4re2XEHufwU0/f6wtatnC4vxgBpVY1wsIdWvp8STKtIAaSHSI TJNfyEug2sCU+yKEzgDSX2qpPrjh2xiScrsR5kClILXZ6Jl3HMMib5/a04nveLL0S1//5h6tDd4 Ylee4wDlbccno2+iATSs38BNOAX3yzQkE10hFF1pfKzczw563Tg3uof52gLYh18pdb7YqMhB0Fk OLN/b6wFvuzdr/EBWKOe6XNplpnFSQ== X-Authority-Analysis: v=2.4 cv=Sf36t/Ru c=1 sm=1 tr=0 ts=68da03bd cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=YGGbjFxyX1jBzPa45jwK0A==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=fESiJu-7EXqA1LiMi5MA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-29_01,2025-09-26_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 suspectscore=0 adultscore=0 spamscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 phishscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2509150000 definitions=main-2509270043 On 9/25/2025 1:48 PM, Krzysztof Kozlowski wrote: > On Thu, 25 Sept 2025 at 15:34, Pankaj Patil > wrote: >> >> From: Taniya Das >> >> Support the display clock controller for GLYMUR SoC. > > One clock controller is not a separate commit. > > Stop inflating patch count, you just makes it difficult for us to see > complete picture. > Sorry about that Krzysztof. As the display clock controller was enabled later point of time probably it was kept as a separate patch and not merged. > Is this somehow for LWN stats? That's why one node per patch? > That is definitely not the intention. As it was enabled later, it was left as a separate patch. -- Thanks, Taniya Das