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([2001:b07:6468:f312:63a7:c72e:ea0e:6045]) by smtp.googlemail.com with ESMTPSA id p5-20020a5d4e05000000b002d75909c76esm20275639wrt.73.2023.03.28.02.20.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 28 Mar 2023 02:20:36 -0700 (PDT) Message-ID: Date: Tue, 28 Mar 2023 11:20:34 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v2] KVM: x86/pmu: Fix emulation on Intel counters' bit width Content-Language: en-US To: Like Xu Cc: Sean Christopherson , kvm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20230322093117.48335-1-likexu@tencent.com> <871434fe-ae80-bec6-9920-a6411f5842c0@gmail.com> From: Paolo Bonzini In-Reply-To: <871434fe-ae80-bec6-9920-a6411f5842c0@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 3/28/23 11:16, Like Xu wrote: > > > If IA32_PERF_CAPABILITIES.FW_WRITE[bit 13] =1, each IA32_PMCi is > accompanied by a > corresponding alias address starting at 4C1H for IA32_A_PMC0. > > The bit width of the performance monitoring counters is specified in > CPUID.0AH:EAX[23:16]. > If IA32_A_PMCi is present, the 64-bit input value (EDX:EAX) of WRMSR to > IA32_A_PMCi will cause > IA32_PMCi to be updated by: > >     COUNTERWIDTH = >         CPUID.0AH:EAX[23:16] bit width of the performance monitoring > counter >     IA32_PMCi[COUNTERWIDTH-1:32] := EDX[COUNTERWIDTH-33:0]); >     IA32_PMCi[31:0] := EAX[31:0]; >     EDX[63:COUNTERWIDTH] are reserved > > --- > > Some might argue that this is all talking about GP counters, not > fixed counters. In fact, the full-width write hw behaviour is > presumed to do the same thing for all counters. But the above behavior, and the #GP, is only true for IA32_A_PMCi (the full-witdh MSR). Did I understand correctly that the behavior for fixed counters is changed without introducing an alias MSR? Paolo