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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b935aee3ab4sm870864166b.61.2026.03.05.02.02.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Mar 2026 02:02:10 -0800 (PST) Message-ID: Date: Thu, 5 Mar 2026 11:02:08 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 7/7] arm64: dts: qcom: Drop CPU masks from GICv3 PPI interrupts To: Geert Uytterhoeven , Marc Zyngier , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Peter Griffin , =?UTF-8?Q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Alim Akhtar , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Dinh Nguyen , Bjorn Andersson , Konrad Dybcio , Thierry Reding Cc: linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-samsung-soc@vger.kernel.org, imx@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org References: <226c5d1005a6e295e0581b2c89e5510dbb7aa9d1.1772643434.git.geert+renesas@glider.be> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <226c5d1005a6e295e0581b2c89e5510dbb7aa9d1.1772643434.git.geert+renesas@glider.be> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: RIpcWyVssL3Gey0Lst6px7CvolZQwp-0 X-Authority-Analysis: v=2.4 cv=BNK+bVQG c=1 sm=1 tr=0 ts=69a954a4 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=QiSWx1vRvZ7C5zKyDnUA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA1MDA4MCBTYWx0ZWRfX//wXG003R0te UR6uJxRORUzivYc2nsCPGhOyEsuodKl5A6m1Z9fbSkoADrKl4lfvZcv8Kqg5GIYC7AN2yQSmr/s 7rzZFOJIEynL2qPpCGvzeNx6Rcip7JZSEb7TfNtZPwT3TKUgh3t/StSMQ5VoLehUuJNd0Un2Zut hXtw+iXwkUmj9kzly9rFfHo0WQ9NxwhYutw+nHtV6nPJBeMhYAPuhPeZ8NTbN4evXLI5mJn2HOf 0x7toM2AtIL9H/rQBIQNb4TCNJY8xJXx95v5QL4ON0xxeKvGj2UViFfw9QrdgAemM70jSCVBtOe DVFvct1QNi/Z1v363pnQB7gJNnLbnz86+cDGaKj/M+8RjEnV5uJtLoPf+rMCIB38AsVGY/BVCWj Nb1U+LZTSNjKsYl4q+yicGLGdaUIDmU6ltYUTNeSUP937w8iwyhGOMs3GMIOiNjt3xY0CLYinZ3 AvNg/cLYsLSfVcV1a0g== X-Proofpoint-ORIG-GUID: RIpcWyVssL3Gey0Lst6px7CvolZQwp-0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-05_02,2026-03-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 spamscore=0 clxscore=1015 impostorscore=0 adultscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603050080 On 3/4/26 6:11 PM, Geert Uytterhoeven wrote: > Unlike older GIC variants, the GICv3 DT bindings do not support > specifying a CPU mask in PPI interrupt specifiers. Drop the masks. > > Signed-off-by: Geert Uytterhoeven > --- Reviewed-by: Konrad Dybcio Konrad