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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae053ecbda9sm698877366b.48.2025.06.23.05.31.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 23 Jun 2025 05:31:17 -0700 (PDT) Message-ID: Date: Mon, 23 Jun 2025 14:31:14 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V3 2/4] dt-bindings: mmc: controller: Add max-sd-hs-frequency property To: Krzysztof Kozlowski , Konrad Dybcio , Sarthak Garg , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Adrian Hunter Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_cang@quicinc.com, quic_nguyenb@quicinc.com, quic_rampraka@quicinc.com, quic_pragalla@quicinc.com, quic_sayalil@quicinc.com, quic_nitirawa@quicinc.com, quic_bhaskarv@quicinc.com, kernel@oss.qualcomm.com References: <20250618072818.1667097-1-quic_sartgarg@quicinc.com> <20250618072818.1667097-3-quic_sartgarg@quicinc.com> <6040afd9-a2a8-49f0-85e9-95257b938156@kernel.org> <9627ed6f-2bb8-40b0-b647-5f659d87f2f9@oss.qualcomm.com> <5bdae07b-a7b1-49be-b843-1704981bc63b@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=YoEPR5YX c=1 sm=1 tr=0 ts=68594917 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=6IFa9wvqVegA:10 a=jqoZUo8hMgpNG5C4G1UA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-ORIG-GUID: uJRMhldcgL5vSpWHcMrn1uVDsMa_nVhA X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjIzMDA3NSBTYWx0ZWRfXzm8X92QZ354L rqswQrnIvmugxFEtLThzinQwz1jdzaqjpZepnQkrh1ny6fga4baoJ0NCp9wgf/X8xzySQvciFRL 7ArUAwFuH7focczSkUUDqiC3nrkHpppXUH3rsJDtIhBfU+HYXb0AUeOnPAT7XLyiKVJO1kjYCeA HGJ21ice2sugmueSKL7WbMF18qBXMWCKSKYakvXceZov63f4cZOD8OIHrL7rZVQmuEyEpboYZZ0 sD6cHlhQ4rS5tO5Z9EmgM0LIaO813Ic1QOqiRpltMTb+pQDgEK9OjGgPyRIPXFjMGwu+PDToSGR Fc/Htq9UaBc4SgA2MTycbvPgUNUA2q0mJipXtCA57FRNoEOmGl2U7mzWM0fKOSAPY2oVOUUI/+i YXywrUb8ts62gu1rgr5Kk6o+Qh5MG7CeDzSH6P9nQ5T9eM/4YyASRs1wkbv1wfEpwHgnpBCa X-Proofpoint-GUID: uJRMhldcgL5vSpWHcMrn1uVDsMa_nVhA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-23_03,2025-06-23_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 mlxscore=0 adultscore=0 suspectscore=0 malwarescore=0 mlxlogscore=999 spamscore=0 bulkscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506230075 On 6/23/25 2:16 PM, Krzysztof Kozlowski wrote: > On 23/06/2025 14:08, Konrad Dybcio wrote: >>>>> >>>>> This might be fine, but your DTS suggests clearly this is SoC compatible >>>>> deducible, which I already said at v1. >>>> >>>> I don't understand why you're rejecting a common solution to a problem >>>> that surely exists outside this one specific chip from one specific >>>> vendor, which may be caused by a multitude of design choices, including >>>> erratic board (not SoC) electrical design >>> >>> No one brought any arguments so far that common solution is needed. The >>> only argument provided - sm8550 - is showing this is soc design. >>> >>> I don't reject common solution. I provided review at v1 to which no one >>> responded, no one argued, no one provided other arguments. >> >> Okay, so the specific problem that causes this observable limitation >> exists on SM8550 and at least one more platform which is not upstream >> today. It can be caused by various electrical issues, in our specific >> case by something internal to the SoC (but external factors may apply >> too) >> >> Looking at the docs, a number of platforms have various limitations >> with regards to frequency at specific speed-modes, some of which seem >> to be handled implicitly by rounding in the clock framework's >> round/set_rate(). >> >> I can very easily imagine there are either boards or platforms in the >> wild, where the speed must be limited for various reasons, maybe some >> of them currently don't advertise it (like sm8550 on next/master) to >> hide that > > But there are no such now. The only argument (fact) provided in this > patchset is: this is issue specific to SM8550 SoC, not the board. See > last patch. Therefore this is compatible-deducible and this makes > property without any upstream user. When one appears, we will have to carry code to repeat what the property does, based on a specific compatible.. And all OS implementations will have to do the same, instead of parsing the explicit information Konrad