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[91.159.24.186]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5aebe33ce5asm513831e87.21.2026.06.30.05.41.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 30 Jun 2026 05:41:36 -0700 (PDT) Message-ID: Date: Tue, 30 Jun 2026 15:41:36 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] arm64: dts: qcom: sm8550: add SDHC4 controller node To: Konrad Dybcio , William Bright Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ram Boukobza , Tendai Makumire References: <20260427-sm8550-sdhc4-support-v2-1-a4241f43ecd5@imd-tec.com> <5a5cbf8f-07ef-419a-8d30-c1b0b2786312@linaro.org> <00643a25-040a-4bec-8324-f52b30d84f9f@linaro.org> From: Vladimir Zapolskiy In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 6/30/26 14:09, Konrad Dybcio wrote: > On 6/12/26 11:11 AM, Vladimir Zapolskiy wrote: >> On 6/12/26 11:47, William Bright wrote: >>> On Thu, Jun 11, 2026 at 10:48:34AM +0300, Vladimir Zapolskiy wrote: >>>> Looks like the SDHC driver behaves expectedly then. For me it's hard to say >>>> what may be the rootcause, I believe the lower bus frequency should be fine, >>>> so it sounds like a hardware issue, but could it be PCB/board specific one? >>>> >>>> If you find a chance to copy the SDHC driver (and its small dependencies) >>>> from Android and test it on your board, and if it also fails, then it might >>>> be well concluded that something is wrong with hardware, still it won't be >>>> quite convincing that the SoC SDHC is to blame here. >>>> >>>> Hope it helps. >>>> >>> My colleague Tendai () had the same issue >>> with dll-tuning failing in SDR50 when working on the downstream 5.15 msm >>> kernel [1]. > > I have a "feature table" and it says SM8550->SDC4->DLL [Y/N] -> No > > no wonder it fails the tuning if it's not present (or that's at least > my interpretation of this doc..) So, is it a hardware problem of the SDHC4 controller, which reports "SDR50 mode requires tuning" bit in CAPS1 (see SDHCI_USE_SDR50_TUNING from sdhci.h)? https://lore.kernel.org/linux-arm-msm/aik1ZYUT-cnpfdQn@will-Legion-Slim-5-16APH8/ > There's some notes about the frequency being limited to 75 MHz in > SDR50 and to 37.5 in DDR50. > > The supported modes are DS, HS, SDR12, SDR25, SDR50 and DDR50 (with > the caveat above). > -- Best wishes, Vladimir