From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65CF3C433EF for ; Wed, 4 May 2022 12:46:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235732AbiEDMuQ (ORCPT ); Wed, 4 May 2022 08:50:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349960AbiEDMuL (ORCPT ); Wed, 4 May 2022 08:50:11 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8EA812CE37; Wed, 4 May 2022 05:46:34 -0700 (PDT) X-UUID: ff51b7b729c14e0596b313d43118dd51-20220504 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:7cb0b557-e4f6-4203-a9cd-3b6a0786fdd6,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,ACT ION:release,TS:45 X-CID-INFO: VERSION:1.1.4,REQID:7cb0b557-e4f6-4203-a9cd-3b6a0786fdd6,OB:0,LOB: 0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,ACTIO N:release,TS:45 X-CID-META: VersionHash:faefae9,CLOUDID:81522c16-2e53-443e-b81a-655c13977218,C OID:IGNORED,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,File:nil,QS:0 ,BEC:nil X-UUID: ff51b7b729c14e0596b313d43118dd51-20220504 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1635945887; Wed, 04 May 2022 20:46:28 +0800 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 4 May 2022 20:46:27 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 4 May 2022 20:46:27 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 4 May 2022 20:46:27 +0800 Message-ID: Subject: Re: [PATCH 09/13] clk: mediatek: reset: Export mtk_register_reset_controller symbols From: Rex-BC Chen To: Yassine Oudjana , Matthias Brugger , Stephen Boyd , "Michael Turquette" , Philipp Zabel , Rob Herring , Krzysztof Kozlowski CC: Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , "Tinghan Shen" , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , "Sam Shih" , Bartosz Golaszewski , , , , , Date: Wed, 4 May 2022 20:46:22 +0800 In-Reply-To: <20220504122601.335495-10-y.oudjana@protonmail.com> References: <20220504122601.335495-1-y.oudjana@protonmail.com> <20220504122601.335495-10-y.oudjana@protonmail.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 2022-05-04 at 16:25 +0400, Yassine Oudjana wrote: > From: Yassine Oudjana > > Export mtk_register_reset_controller and > mtk_register_reset_controller_set_clr to support building reset > drivers as modules. > > Signed-off-by: Yassine Oudjana > --- > drivers/clk/mediatek/reset.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/clk/mediatek/reset.c > b/drivers/clk/mediatek/reset.c > index bcec4b89f449..6c2effe6afef 100644 > --- a/drivers/clk/mediatek/reset.c > +++ b/drivers/clk/mediatek/reset.c > @@ -129,6 +129,7 @@ void mtk_register_reset_controller(struct > device_node *np, > mtk_register_reset_controller_common(np, num_regs, regofs, > &mtk_reset_ops); > } > +EXPORT_SYMBOL_GPL(mtk_register_reset_controller); > > void mtk_register_reset_controller_set_clr(struct device_node *np, > unsigned int num_regs, int regofs) > @@ -136,5 +137,6 @@ void mtk_register_reset_controller_set_clr(struct > device_node *np, > mtk_register_reset_controller_common(np, num_regs, regofs, > &mtk_reset_ops_set_clr); > } > +EXPORT_SYMBOL_GPL(mtk_register_reset_controller_set_clr); > > MODULE_LICENSE("GPL"); Hello Yassine, Thanks for your patch for mediatek clk reset. But I have another series to cleanup mediatek clk reset drivers and most of my patches are reviewed. Please refer to https://patchwork.kernel.org/project/linux-mediatek/list/?series=637849 BRs, Rex