From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from vps0.lunn.ch (vps0.lunn.ch [156.67.10.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8548329BDA2; Mon, 27 Oct 2025 01:44:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=156.67.10.101 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761529451; cv=none; b=Lq12efr/y0YRhRnTw+fTkvxddCT8UjEF5LiELAkVh1H/Gy4iWCI/NFde7/AyF42qowUXKYSqT+vOc3Ot94+qwUY6VL4OG5XOU1WvxPbJRV/ZVJWIGkncAX3+KZKVWhXsPPLhhHxx+4sqlr0uIWkAWHMUj+NPjAiXi/9AODcbrSI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761529451; c=relaxed/simple; bh=E+QMND24/WP/zTvdXff8gp6hTMK1AKq41bsw0S6dp8w=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=KuuxdwhnbT3c/kxNgdsNbD4PYAe4+rAq4+nkDV3FdKfb+StbzHvdlQBravoiqlMk1NsiEhA4F28+WO6+3lS7u3vKlf8HqJkP8xkDXpnixEAgZXtgz/nsjAAskxMSwwdzX2rNaJ9aWhcQVPA3NUJVhUVgkdD3aLO0X+7ccmufKfY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch; spf=pass smtp.mailfrom=lunn.ch; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b=vqKT+cw7; arc=none smtp.client-ip=156.67.10.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=lunn.ch Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b="vqKT+cw7" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=7a/EwuumQpo2swNq1SpUCucENGWBvUDAitJ2riFGT+Q=; b=vqKT+cw7qfCksSfiPz3S4iHhrx VA30MsXAzH6jQu6JS9fR8f45Gp3ooOLXKwGx4yGeJiduyc1fWA+bZflGabd8ESumpM+8PMl/qaSGX uoGN3n/PJTTN/Ovs+5D16m3RoKgoPXO3stpKVCzTFxGasaOu5qvgLwseqVQbSNm4OKMI=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1vDCGa-00C9BP-I8; Mon, 27 Oct 2025 02:43:24 +0100 Date: Mon, 27 Oct 2025 02:43:24 +0100 From: Andrew Lunn To: Ryan Chen Cc: Arnd Bergmann , BMC-SW , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Jeremy Kerr , Lee Jones , Catalin Marinas , Will Deacon , Bjorn Andersson , Geert Uytterhoeven , Nishanth Menon , =?iso-8859-1?Q?N=EDcolas_F=2E_R=2E_A=2E?= Prado , Taniya Das , "Lad, Prabhakar" , Kuninori Morimoto , Eric Biggers , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-aspeed@lists.ozlabs.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v6 4/6] arm64: dts: aspeed: Add initial AST2700 SoC device tree Message-ID: References: <20251022070543.1169173-1-ryan_chen@aspeedtech.com> <20251022070543.1169173-5-ryan_chen@aspeedtech.com> <6a97fbb4-19c2-4ffa-9c73-26aea02c27e4@app.fastmail.com> <71df9bdf-53b2-45e2-a9e3-5b00a556f957@lunn.ch> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: > SoC0, referred to as the CPU die, contains a dual-core Cortex-A35 > cluster and two Cortex-M4 cores, along with its own clock/reset > domains and high-speed peripheral set. > SoC1, referred to as the I/O die, contains the Boot MCU and its own > clock/reset domains and low-speed peripheral set, and is responsible > for system boot and control functions. So is the same .dtsi file shared by both systems? How do you partition devices so each CPU cluster knows it has exclusive access to which peripherals? Seems like a fun system to play core wars on. Andrew