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Wed, 15 Oct 2025 12:43:05 -0700 From: Nicolin Chen To: , CC: , , , , , , , , , , Subject: [PATCH v3 4/7] iommu/arm-smmu-v3: Pre-allocate a per-master invalidation array Date: Wed, 15 Oct 2025 12:42:49 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000A6734:EE_|IA0PR12MB7721:EE_ X-MS-Office365-Filtering-Correlation-Id: 46c31705-cdd4-4f01-570f-08de0c231a67 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?0KtqQmSfGamPh8c9n+2c/A5XXM+imxeaUpHvQIU0+rWl/2ykIHEfgc8X3ikH?= =?us-ascii?Q?3mbghBfKR3XnPd7o6NOPbEvSZjoiXRGhMVnHhaMREXJx9kIrOEgEM9Zn8+J7?= =?us-ascii?Q?T/G1A0LLgR0q82EfrZqBgWuf5N1ZDA/MEJ0FNIcAPzpx7BI44vbmMm+jK4Ti?= =?us-ascii?Q?0y8bbm8qAy1JaOxRgmBfPTJQKuPZLUanIhUrzUjyhOXJTPYhx9haZMs2zn6l?= =?us-ascii?Q?En28tfkLcIrPqb6PGfRJ9cxUQxvRGjhCAa9qMt9sbxClubteGBcqvaec6XGH?= =?us-ascii?Q?hUTtnFS0s2Ow3xaf5vU9Svim6J9DjUJxtyjEGCxNt2Ct+nLH3kz78Bp/J7I/?= =?us-ascii?Q?wZ26sx5KknXj+NzRhY/1Am51FF2lQYFwyhwgWFaVJenmGd/HadvDzl5S7J9b?= =?us-ascii?Q?VKU9Fup/tz29DuXXvTqF0LcLHmOsW/ZMex5QsiNHh3xVQRH3fbGkCmakA7GC?= =?us-ascii?Q?s9HbyyNvHk5002NQC2nYfQ0643kzmpwX0Xlvql7KoaB8Je3fsxk29Ib7wSAv?= =?us-ascii?Q?jeB7/97KhvVzhBMeSIszcqqDGebYEV6wVkERrsHFjGS5ZZzXCJXpAyHrs/SQ?= =?us-ascii?Q?wwLWRLxl9hCNBF89Ilx5LA0QY4md8rGzhLszRZ3vpo+rxYAaCTmaFx/n6sJx?= =?us-ascii?Q?6KZOmM5V0pnQsqAfVbo2yK9wukEC8kgf7ppK/MdW/daUt9UDmsUPICsd5CDw?= =?us-ascii?Q?RrOtb44BRhOk//kD4+VsChUi9KdKwu+zq0OZdzZyZsb5Mqhqs7NNFneQeA31?= =?us-ascii?Q?GOHXvSl/TF01Pk4Q/Lga75fImnnGNdwt+3ClkRzA/+RRSxa9V1p+b3uyBpUU?= =?us-ascii?Q?U0pSPc124BCN0XEozJXXmSyDWApcLc1OcYKurmi+pj5/4t5ev0Wpp0r4uNjS?= =?us-ascii?Q?QwNCsrz0WFo+akLIDupminWk1c6tDSZSngpCSkxL8m6Ki3DO2jNc7sVYal55?= =?us-ascii?Q?iVN4OQeM4K7AdyREzdMvi6UD7gj5qlMIFAqWYjKiLK6QMThmfIOt7QKApnNi?= =?us-ascii?Q?thoLINlSOq94azo6o16WKs0J2H99in7a1KmlXNMRfBl6IAW6dl6VIYDem+V+?= =?us-ascii?Q?9dwFfqXKAwaIUHlbLO9kp72kAazrl4cvgxoNkpyBPQ5PF3Z6HIulC3D3POdx?= =?us-ascii?Q?NceGcp/Cp+ZAmSkIE0yPnoGgvOHQ1OuylI+RtjaT4QRiql+1EIY09AWlsD8a?= =?us-ascii?Q?z2yBeoJb2y4FPIjkTqPN2fh1l+FcfhRgn9SushT6Ec3jAD3B2qiICTRM/eqL?= =?us-ascii?Q?nQbVsM1I5cnkyiU5/my0bo4ooWWBAbxqotgIdY9yQ/9oVeaLUjIvxKocKHlo?= =?us-ascii?Q?wNCO2EV/ItMXprqVlL4P3jY55FoJhNs0g/233VxoV78rZNE/DzVvNQoM7rYe?= =?us-ascii?Q?1nYoRgarX7GvmkZgQGmpBhF78jCKOTs/Tc8xDWp8IJLCx1bS4AdjS7hjRkjA?= =?us-ascii?Q?J0guHYvl2AT+BpRC9zu2J5hrLhwOxkDDOcggd4u6AAt5HPjzE55BBxxld4gF?= =?us-ascii?Q?FXJ97nlN6Qj9bpPAz4WN0xBnyhikox9SXXPF2AwoRZD8GHQuNRjX+kNJtLFl?= =?us-ascii?Q?cDGRi9vnSjjRmreFHP0=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Oct 2025 19:43:23.8110 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 46c31705-cdd4-4f01-570f-08de0c231a67 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A6734.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7721 When a master is attached from an old domain to a new domain, it needs to build an invalidation array to delete and add the array entries from/onto the invalidation arrays of those two domains, passed via the to_merge and to_unref arguments into arm_smmu_invs_merge/unref() respectively. Since the master->num_streams might differ across masters, a memory would have to be allocated when building an to_merge/to_unref array which might fail with -ENOMEM. On the other hand, an attachment to arm_smmu_blocked_domain must not fail so it's the best to avoid any memory allocation in that path. Pre-allocate a fixed size invalidation array for every master. This array will be used as a scratch to fill dynamically when building a to_merge or to_unref invs array. Sort fwspec->ids in an ascending order to fit to the arm_smmu_invs_merge() function. Co-developed-by: Jason Gunthorpe Signed-off-by: Jason Gunthorpe Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 8 ++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 27 +++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index d079c66a41e94..c43b2ffef8a4d 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -930,6 +930,14 @@ struct arm_smmu_master { struct arm_smmu_device *smmu; struct device *dev; struct arm_smmu_stream *streams; + /* + * Scratch memory for a to_merge or to_unref array to build a per-domain + * invalidation array. It'll be pre-allocated with enough enries for all + * possible build scenarios. It can be used by only one caller at a time + * until the arm_smmu_invs_merge/unref() finishes. Must be locked by the + * iommu_group mutex. + */ + struct arm_smmu_invs *build_invs; struct arm_smmu_vmaster *vmaster; /* use smmu->streams_mutex */ /* Locked by the iommu core using the group mutex */ struct arm_smmu_ctx_desc_cfg cd_table; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 2a8a0c76af67b..97f52130992cd 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3687,12 +3687,22 @@ static int arm_smmu_init_sid_strtab(struct arm_smmu_device *smmu, u32 sid) return 0; } +static int arm_smmu_ids_cmp(const void *_l, const void *_r) +{ + const typeof_member(struct iommu_fwspec, ids[0]) *l = _l; + const typeof_member(struct iommu_fwspec, ids[0]) *r = _r; + + return cmp_int(*l, *r); +} + static int arm_smmu_insert_master(struct arm_smmu_device *smmu, struct arm_smmu_master *master) { int i; int ret = 0; struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(master->dev); + bool ats_supported = dev_is_pci(master->dev) && + pci_ats_supported(to_pci_dev(master->dev)); master->streams = kcalloc(fwspec->num_ids, sizeof(*master->streams), GFP_KERNEL); @@ -3700,6 +3710,21 @@ static int arm_smmu_insert_master(struct arm_smmu_device *smmu, return -ENOMEM; master->num_streams = fwspec->num_ids; + if (!ats_supported) { + /* Base case has 1 ASID entry or maximum 2 VMID entries */ + master->build_invs = arm_smmu_invs_alloc(2); + } else { + /* Put the ids into order for sorted to_merge/to_unref arrays */ + sort_nonatomic(fwspec->ids, fwspec->num_ids, + sizeof(fwspec->ids[0]), arm_smmu_ids_cmp, NULL); + /* ATS case adds num_ids of entries, on top of the base case */ + master->build_invs = arm_smmu_invs_alloc(2 + fwspec->num_ids); + } + if (IS_ERR(master->build_invs)) { + kfree(master->streams); + return PTR_ERR(master->build_invs); + } + mutex_lock(&smmu->streams_mutex); for (i = 0; i < fwspec->num_ids; i++) { struct arm_smmu_stream *new_stream = &master->streams[i]; @@ -3737,6 +3762,7 @@ static int arm_smmu_insert_master(struct arm_smmu_device *smmu, for (i--; i >= 0; i--) rb_erase(&master->streams[i].node, &smmu->streams); kfree(master->streams); + kfree(master->build_invs); } mutex_unlock(&smmu->streams_mutex); @@ -3758,6 +3784,7 @@ static void arm_smmu_remove_master(struct arm_smmu_master *master) mutex_unlock(&smmu->streams_mutex); kfree(master->streams); + kfree(master->build_invs); } static struct iommu_device *arm_smmu_probe_device(struct device *dev) -- 2.43.0