From: Dave Jiang <dave.jiang@intel.com>
To: Neeraj Kumar <s.neeraj@samsung.com>,
dan.j.williams@intel.com, dave@stgolabs.net,
jonathan.cameron@huawei.com, alison.schofield@intel.com,
vishal.l.verma@intel.com, ira.weiny@intel.com
Cc: a.manzanares@samsung.com, nifan.cxl@gmail.com,
anisa.su@samsung.com, vishak.g@samsung.com,
krish.reddy@samsung.com, arun.george@samsung.com,
alok.rathore@samsung.com, neeraj.kernel@gmail.com,
linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org,
nvdimm@lists.linux.dev, gost.dev@samsung.com, cpgs@samsung.com
Subject: Re: [RFC PATCH 14/20] cxl/region: Add cxl pmem region creation routine for region persistency
Date: Thu, 10 Jul 2025 08:59:15 -0700 [thread overview]
Message-ID: <fdc06026-c681-4dae-9202-ad89293931a5@intel.com> (raw)
In-Reply-To: <1691538257.61750165382463.JavaMail.epsvc@epcpadp2new>
On 6/17/25 5:39 AM, Neeraj Kumar wrote:
> Added exported cxl_create_pmem_region routine to create cxl pmem region
> from LSA parsed cxl region information.
> Inspirition for the function is taken from ndctl device attribute
> (_store) call. It allocates cxlr and fills information parsed from LSA
> and calls device_add(&cxlr->dev) to initiates further region creation
> porbes
>
> Signed-off-by: Neeraj Kumar <s.neeraj@samsung.com>
> ---
> drivers/cxl/core/port.c | 6 ++
> drivers/cxl/core/region.c | 208 ++++++++++++++++++++++++++++++++++++++
> drivers/cxl/cxl.h | 11 ++
> 3 files changed, 225 insertions(+)
>
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index bca668193c49..2452f7c15b2d 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -2150,6 +2150,12 @@ void cxl_bus_drain(void)
> }
> EXPORT_SYMBOL_NS_GPL(cxl_bus_drain, "CXL");
>
> +void cxl_wq_flush(void)
> +{
> + flush_workqueue(cxl_bus_wq);
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_wq_flush, "CXL");
> +
> bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd)
> {
> return queue_work(cxl_bus_wq, &cxlmd->detach_work);
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index b98b1ccffd1c..8990e3c3474d 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -2522,6 +2522,214 @@ static ssize_t create_ram_region_show(struct device *dev,
> return __create_region_show(to_cxl_root_decoder(dev), buf);
> }
>
> +static ssize_t update_region_size(struct cxl_region *cxlr, u64 val)
Maybe call it resize_or_free_region_hpa()?
Also rename 'val' to 'size'
> +{
> + int rc;
> +
> + rc = down_write_killable(&cxl_region_rwsem);
> + if (rc)
> + return rc;
> +
> + if (val)
> + rc = alloc_hpa(cxlr, val);
> + else
> + rc = free_hpa(cxlr);
> + up_write(&cxl_region_rwsem);
> +
> + if (rc)
> + return rc;
> +
> + return 0;
> +}
Share common code with core/region.c:size_store(). Please use helper function and not duplicate code.
> +
> +static ssize_t update_region_dpa_size(struct cxl_region *cxlr,
resize_or_free_dpa()
> + struct cxl_decoder *cxld,
> + unsigned long long size)
u64 size
> +{
> + int rc;
> + struct cxl_endpoint_decoder *cxled =
> + to_cxl_endpoint_decoder(&cxld->dev);
> +
> + if (!IS_ALIGNED(size, SZ_256M))
> + return -EINVAL;
> +
> + rc = cxl_dpa_free(cxled);
> + if (rc)
> + return rc;
> +
> + if (size == 0)
> + return 0;
> +
> + rc = cxl_dpa_alloc(cxled, size);
> + if (rc)
> + return rc;
> +
> + return 0;
> +}
Share common code with core/port.c:dpa_size_store(). Please use helper function and not duplicate code.
> +
> +static ssize_t update_region_dpa_mode(struct cxl_region *cxlr,
> + struct cxl_decoder *cxld)
> +{
> + int rc;
> + struct cxl_endpoint_decoder *cxled =
> + to_cxl_endpoint_decoder(&cxld->dev);
> +
> + rc = cxl_dpa_set_mode(cxled, CXL_DECODER_PMEM);
Don't think CXL_DECODER_PMEM exists any longer. It's CXL_PARTMODE_PMEM. Just beware there have been some changes while you are rebasing to the latest upstream code.
> + if (rc)
> + return rc;
> +
> + return 0;
> +}
> +
> +static size_t attach_region_target(struct cxl_region *cxlr,
> + struct cxl_decoder *cxld, int pos)
> +{
> + int rc;
> + struct cxl_endpoint_decoder *cxled =
> + to_cxl_endpoint_decoder(&cxld->dev);
> +
> + rc = attach_target(cxlr, cxled, pos, TASK_INTERRUPTIBLE);
> +
> + if (rc < 0)
> + return rc;
> +
> + return 0;
> +}
> +
> +static ssize_t commit_region(struct cxl_region *cxlr)
> +{
> + struct cxl_region_params *p = &cxlr->params;
> + ssize_t rc;
> +
> + rc = down_write_killable(&cxl_region_rwsem);
> + if (rc)
> + return rc;
> +
> + /* Already in the requested state? */
> + if (p->state >= CXL_CONFIG_COMMIT)
> + goto out;
> +
> + /* Not ready to commit? */
> + if (p->state < CXL_CONFIG_ACTIVE) {
> + rc = -ENXIO;
> + goto out;
> + }
> +
> + /*
> + * Invalidate caches before region setup to drop any speculative
> + * consumption of this address space
> + */
> + rc = cxl_region_invalidate_memregion(cxlr);
> + if (rc)
> + goto out;
> +
> + rc = cxl_region_decode_commit(cxlr);
> + if (rc == 0)
> + p->state = CXL_CONFIG_COMMIT;
> +out:
> + up_write(&cxl_region_rwsem);
> + if (rc)
> + return rc;
> + return 0;
> +}
Sharing common code with core/region.c:commit_store()?
> +
> +static struct cxl_region *
> +devm_cxl_pmem_add_region(struct cxl_root_decoder *cxlrd,
> + struct cxl_decoder *cxld,
> + struct cxl_pmem_region_params *params, int id,
> + enum cxl_decoder_mode mode, enum cxl_decoder_type type)
> +{
> + struct cxl_port *port;
> + struct cxl_region *cxlr;
> + struct cxl_region_params *p;
> + struct device *dev;
> + int rc;
> +
> + if (!cxlrd)
> + return ERR_PTR(-EINVAL);
> +
> + port = to_cxl_port(cxlrd->cxlsd.cxld.dev.parent);
> +
> + cxlr = cxl_region_alloc(cxlrd, id);
> + if (IS_ERR(cxlr))
> + return cxlr;
> + cxlr->mode = mode;
> + cxlr->type = type;
> +
> + dev = &cxlr->dev;
> + rc = dev_set_name(dev, "region%d", id);
> + if (rc)
> + goto err;
> +> + p = &cxlr->params;
> + p->uuid = params->uuid;
> + p->interleave_ways = params->nlabel;
> + p->interleave_granularity = params->ig;
> +
> + /* Update region size */
Not sure what value this comment adds
> + if (update_region_size(cxlr, params->rawsize))
> + goto err;
> +
> + /* Flush cxl wq */
Can you explain here why a flush is needed?
> + cxl_wq_flush();
> +
> + /* Clear DPA Size */
comment provides no value
> + if (update_region_dpa_size(cxlr, cxld, 0))
> + goto err;
> +
> + /* Update DPA mode */
same as above
> + if (update_region_dpa_mode(cxlr, cxld))
> + goto err;
> +
> + /* Update DPA Size */
same as above
> + if (update_region_dpa_size(cxlr, cxld, params->rawsize))
> + goto err;
> +
> + /* Attach region targets */
same as above
> + if (attach_region_target(cxlr, cxld, params->position))
> + goto err;
> +
> + /* Commit Region */
same as above
> + if (commit_region(cxlr))
> + goto err;
Can you please provide some verbose explanation as to what all these extra steps are doing for pmem versus devm_cxl_add_region() for dram?
> +
> + rc = device_add(dev);
> + if (rc)
> + goto err;
> +
> + rc = devm_add_action_or_reset(port->uport_dev, unregister_region, cxlr);
> + if (rc)
> + return ERR_PTR(rc);
> +
> + dev_dbg(port->uport_dev, "%s: created %s\n",
> + dev_name(&cxlrd->cxlsd.cxld.dev), dev_name(dev));
> + return cxlr;
> +
> +err:
> + put_device(dev);
> + return ERR_PTR(rc);
> +}
> +
> +struct cxl_region *cxl_create_pmem_region(struct cxl_root_decoder *cxlrd,
> + struct cxl_decoder *cxld,
> + struct cxl_pmem_region_params *params, int id)
> +{
> + int rc;
> +
> + rc = memregion_alloc(GFP_KERNEL);
> + if (rc < 0)
> + return ERR_PTR(rc);
> +
> + if (atomic_cmpxchg(&cxlrd->region_id, id, rc) != id) {
> + memregion_free(rc);
> + return ERR_PTR(-EBUSY);
> + }
> +
> + return devm_cxl_pmem_add_region(cxlrd, cxld, params, id,
> + CXL_DECODER_PMEM, CXL_DECODER_HOSTONLYMEM);
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_create_pmem_region, "CXL");
Can __create_region() be modified to determine whether to create dram region or pmem?
DJ
> +
> static struct cxl_region *__create_region(struct cxl_root_decoder *cxlrd,
> enum cxl_decoder_mode mode, int id)
> {
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 9423ea3509ad..30c80e04cb27 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -759,6 +759,7 @@ DEFINE_FREE(put_cxl_port, struct cxl_port *, if (!IS_ERR_OR_NULL(_T)) put_device
> int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd);
> void cxl_bus_rescan(void);
> void cxl_bus_drain(void);
> +void cxl_wq_flush(void);
> struct cxl_port *cxl_pci_find_port(struct pci_dev *pdev,
> struct cxl_dport **dport);
> struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd,
> @@ -877,6 +878,9 @@ struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev);
> int cxl_add_to_region(struct cxl_port *root,
> struct cxl_endpoint_decoder *cxled);
> struct cxl_dax_region *to_cxl_dax_region(struct device *dev);
> +struct cxl_region *cxl_create_pmem_region(struct cxl_root_decoder *cxlrd,
> + struct cxl_decoder *cxld,
> + struct cxl_pmem_region_params *params, int id);
> #else
> static inline bool is_cxl_pmem_region(struct device *dev)
> {
> @@ -895,6 +899,13 @@ static inline struct cxl_dax_region *to_cxl_dax_region(struct device *dev)
> {
> return NULL;
> }
> +static inline struct cxl_region *cxl_create_pmem_region(
> + struct cxl_root_decoder *cxlrd,
> + struct cxl_decoder *cxld,
> + struct cxl_pmem_region_params *params, int id)
> +{
> + return NULL;
> +}
> #endif
>
> void cxl_endpoint_parse_cdat(struct cxl_port *port);
next prev parent reply other threads:[~2025-07-10 15:59 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20250617123944.78345-1-s.neeraj@samsung.com>
[not found] ` <CGME20250617124008epcas5p2e702f786645d44ceb1cdd980a914ce8e@epcas5p2.samsung.com>
2025-06-17 12:39 ` [RFC PATCH 01/20] nvdimm/label: Introduce NDD_CXL_LABEL flag to set cxl label format Neeraj Kumar
2025-06-20 16:40 ` Jonathan Cameron
2025-06-26 9:48 ` Neeraj Kumar
2025-07-02 18:02 ` Ira Weiny
2025-07-03 9:58 ` Neeraj Kumar
2025-07-09 22:57 ` Dave Jiang
2025-07-18 12:13 ` Neeraj Kumar
[not found] ` <CGME20250617124011epcas5p2264e30ec58977907f80d311083265641@epcas5p2.samsung.com>
2025-06-17 12:39 ` [RFC PATCH 02/20] nvdimm/label: Prep patch to accommodate cxl lsa 2.1 support Neeraj Kumar
2025-06-23 10:53 ` Jonathan Cameron
2025-06-26 9:51 ` Neeraj Kumar
2025-07-02 17:55 ` Ira Weiny
2025-07-03 10:04 ` Neeraj Kumar
[not found] ` <CGME20250617124013epcas5p3c241c626448fcf7851a100fdf2816160@epcas5p3.samsung.com>
2025-06-17 12:39 ` [RFC PATCH 03/20] nvdimm/namespace_label: Add namespace label changes as per CXL LSA v2.1 Neeraj Kumar
[not found] ` <CGME20250617124016epcas5p20b04482f41a58c7f83484aa2b8b0c33c@epcas5p2.samsung.com>
2025-06-17 12:39 ` [RFC PATCH 04/20] nvdimm/label: CXL labels skip the need for 'interleave-set cookie' Neeraj Kumar
[not found] ` <CGME20250617124019epcas5p39815cc0f2b175aee40c194625166695c@epcas5p3.samsung.com>
2025-06-17 12:39 ` [RFC PATCH 05/20] nvdimm/region_label: Add region label updation routine Neeraj Kumar
2025-06-23 9:05 ` Jonathan Cameron
2025-06-26 9:54 ` Neeraj Kumar
2025-07-17 22:53 ` Fabio M. De Francesco
2025-07-18 13:00 ` Neeraj Kumar
[not found] ` <CGME20250617124022epcas5p2441d6c5dfaeceb744b5fc00add7ceae0@epcas5p2.samsung.com>
2025-06-17 12:39 ` [RFC PATCH 06/20] nvdimm/region_label: Add region label deletion routine Neeraj Kumar
2025-06-23 9:09 ` Jonathan Cameron
2025-06-26 9:55 ` Neeraj Kumar
[not found] ` <CGME20250617124025epcas5p1ce6656fed9ef1175812f80574048cd7a@epcas5p1.samsung.com>
2025-06-17 12:39 ` [RFC PATCH 07/20] nvdimm/namespace_label: Update namespace init_labels and its region_uuid Neeraj Kumar
2025-06-23 9:11 ` Jonathan Cameron
2025-06-26 9:58 ` Neeraj Kumar
[not found] ` <CGME20250617124028epcas5p2bb45182c91359a16efc5b1561927abce@epcas5p2.samsung.com>
2025-06-17 12:39 ` [RFC PATCH 08/20] nvdimm/label: Include region label in slot validation Neeraj Kumar
2025-06-23 9:13 ` Jonathan Cameron
2025-06-26 10:00 ` Neeraj Kumar
[not found] ` <CGME20250617124031epcas5p3542c2fc6d946f3cdcbc06dbfc65743e2@epcas5p3.samsung.com>
2025-06-17 12:39 ` [RFC PATCH 09/20] nvdimm/namespace_label: Skip region label during ns label DPA reservation Neeraj Kumar
[not found] ` <CGME20250617124034epcas5p2f53c3cc21c51b7c176ad580d5d954c64@epcas5p2.samsung.com>
2025-06-17 12:39 ` [RFC PATCH 10/20] nvdimm/region_label: Preserve cxl region information from region label Neeraj Kumar
[not found] ` <CGME20250617124037epcas5p2efa5e8ac19df70cdeb7330404eed385f@epcas5p2.samsung.com>
2025-06-17 12:39 ` [RFC PATCH 11/20] nvdimm/region_label: Export routine to fetch region information Neeraj Kumar
[not found] ` <CGME20250617124040epcas5p3be044cbdc5b33b0b8465d84870a5b280@epcas5p3.samsung.com>
2025-06-17 12:39 ` [RFC PATCH 12/20] nvdimm/namespace_label: Skip region label during namespace creation Neeraj Kumar
2025-06-23 9:17 ` Jonathan Cameron
2025-06-26 10:02 ` Neeraj Kumar
[not found] ` <CGME20250617124043epcas5p21e5b77aa3a6acfa7e01847ffd58350ed@epcas5p2.samsung.com>
2025-06-17 12:39 ` [RFC PATCH 13/20] cxl/mem: Refactor cxl pmem region auto-assembling Neeraj Kumar
2025-06-23 9:20 ` Jonathan Cameron
2025-06-26 10:03 ` Neeraj Kumar
2025-07-10 0:38 ` Dave Jiang
2025-07-18 12:30 ` Neeraj Kumar
2025-07-21 18:11 ` Dave Jiang
[not found] ` <CGME20250617124046epcas5p16a45d2afe3b41ca08994a5cca09bfb68@epcas5p1.samsung.com>
2025-06-17 12:39 ` [RFC PATCH 14/20] cxl/region: Add cxl pmem region creation routine for region persistency Neeraj Kumar
2025-06-23 9:43 ` Jonathan Cameron
2025-06-26 10:23 ` Neeraj Kumar
2025-07-10 15:59 ` Dave Jiang [this message]
2025-07-18 12:45 ` Neeraj Kumar
[not found] ` <CGME20250617124049epcas5p1de7eeee3b5ddd12ea221ca3ebf22f6e8@epcas5p1.samsung.com>
2025-06-17 12:39 ` [RFC PATCH 15/20] cxl: Add a routine to find cxl root decoder on cxl bus Neeraj Kumar
2025-06-23 9:44 ` Jonathan Cameron
2025-06-26 10:38 ` Neeraj Kumar
2025-06-26 19:19 ` Alison Schofield
2025-06-27 9:03 ` Neeraj Kumar
2025-07-10 16:23 ` Dave Jiang
2025-07-18 12:48 ` Neeraj Kumar
[not found] ` <CGME20250617124052epcas5p24aace8321ed09af8bdd1e8c30c20cd84@epcas5p2.samsung.com>
2025-06-17 12:39 ` [RFC PATCH 16/20] cxl/mem: Preserve cxl root decoder during mem probe Neeraj Kumar
[not found] ` <CGME20250617124055epcas5p4978a3c139128bf5873c60ca0a10f5199@epcas5p4.samsung.com>
2025-06-17 12:39 ` [RFC PATCH 17/20] cxl/pmem: Preserve region information into nd_set Neeraj Kumar
[not found] ` <CGME20250617124058epcas5p2324bd3b1bf95d47f553d90fdc727e50d@epcas5p2.samsung.com>
2025-06-17 12:39 ` [RFC PATCH 18/20] cxl/pmem: Add support of cxl lsa 2.1 support in cxl pmem Neeraj Kumar
2025-06-23 9:48 ` Jonathan Cameron
2025-06-26 10:41 ` Neeraj Kumar
2025-07-10 17:18 ` Dave Jiang
2025-07-18 12:51 ` Neeraj Kumar
2025-07-21 17:44 ` Dave Jiang
[not found] ` <CGME20250617124101epcas5p4d54f34ebc5161b7cb816e352d144d9a1@epcas5p4.samsung.com>
2025-06-17 12:39 ` [RFC PATCH 19/20] cxl/pmem_region: Prep patch to accommodate pmem_region attributes Neeraj Kumar
2025-06-23 9:53 ` Jonathan Cameron
2025-06-26 10:45 ` Neeraj Kumar
[not found] ` <CGME20250617124104epcas5p41105ad63af456b5cdb041e174a99925e@epcas5p4.samsung.com>
2025-06-17 12:39 ` [RFC PATCH 20/20] cxl/pmem_region: Add cxl region label updation and deletion device attributes Neeraj Kumar
2025-06-23 9:56 ` Jonathan Cameron
2025-06-26 10:48 ` Neeraj Kumar
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