From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 94E32322C6D for ; Thu, 16 Jul 2026 08:59:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784192395; cv=none; b=uVjpdwTrDBhkpnWZf8BQuRaldxqRbINK90DpcGE/mLq2R5wTjukG8IT/lkuMRgfa723V6+xKtFCfRt9Gu6peq5mO8z0yf1b+dV3zoi91y0Gy+DGEm/gqlv3WkOJLCTJ455OuGx71OMQ3vELagHBV3vUEBSyZriGCIyzUL8p89vM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784192395; c=relaxed/simple; bh=WnqDKuNfddYN/Kaj7opmABEUWn9nytGfiFO4xnHhk8E=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=YdD5tRHv+hkFbl5iI06+AF6Ma5cr+Krg7eDZN89Vb5De0bzBBcHS0mm3WgXZ2qR+/rRzON5/6nDXVF6zsP+VNmHfxWoLflJjvDgmavy+AyfkBpixe1tjJK+urSgumm0ddv55PJMsVlfo5ei8Yy+15olSbFC7ua0JgsbKXYWoa7k= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=EJtDDnN2; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="EJtDDnN2" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 16CFB339; Thu, 16 Jul 2026 01:59:37 -0700 (PDT) Received: from [10.2.212.8] (e134344.arm.com [10.2.212.8]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 30E2C3F7B4; Thu, 16 Jul 2026 01:59:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784192381; bh=WnqDKuNfddYN/Kaj7opmABEUWn9nytGfiFO4xnHhk8E=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=EJtDDnN24rHUSiGGmieTFjmFUSvnU0EaaFOmncX1LM1HRJxl2+ZmlmuLToWl5mF8g FOWJYZSzp0p6y1X9coW/PcqIFgH19IpZ10rNVBORtvvWS5fZ28/toesa6lmfZqfEJr Il3gU+qT2RDQzZvwnq6k+UqKqEF7LGOzkEvqrdfA= Message-ID: Date: Thu, 16 Jul 2026 09:59:38 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Thunderbird Daily Subject: Re: [PATCH v1 02/11] arm_mpam: Restore the error interrupt enable from mpam_cpu_online() To: Gavin Shan Cc: james.morse@arm.com, reinette.chatre@intel.com, fenghuay@nvidia.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dave.martin@arm.com, andre.przywara@arm.com References: <20260710115546.29644-1-ben.horgan@arm.com> <20260710115546.29644-3-ben.horgan@arm.com> <519cddd8-d67a-4aef-afdf-97c933b73f82@redhat.com> Content-Language: en-US From: Ben Horgan In-Reply-To: <519cddd8-d67a-4aef-afdf-97c933b73f82@redhat.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hi Gavin, On 7/16/26 04:59, Gavin Shan wrote: > Hi Ben, > > On 7/10/26 9:55 PM, Ben Horgan wrote: >> When all CPUs affine to an MSC are offline the MSC may lose register state >> which the driver then restores when an affine CPU comes back online. The >> error interrupt enable, MPAMF_ECR.INTEN, is missed. >> >> Restore MPAMF_ECR at CPU online. >> >> Fixes: 49aa621c4dca ("arm_mpam: Register and enable IRQs") >> Signed-off-by: Ben Horgan >> --- >>   drivers/resctrl/mpam_devices.c | 8 +++++++- >>   1 file changed, 7 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c >> index 82966ca2a631..acfa9a4dc2fc 100644 >> --- a/drivers/resctrl/mpam_devices.c >> +++ b/drivers/resctrl/mpam_devices.c >> @@ -1852,8 +1852,14 @@ static int mpam_cpu_online(unsigned int cpu) >>           if (msc->reenable_error_ppi) >>               _enable_percpu_irq(&msc->reenable_error_ppi); >>   -        if (atomic_fetch_inc(&msc->online_refs) == 0) >> +        if (atomic_fetch_inc(&msc->online_refs) == 0) { >> +            mutex_lock(&msc->error_irq_lock); >> +            if (msc->error_irq_hw_enabled) >> +                mpam_touch_msc(msc, mpam_enable_msc_ecr, msc); >> +            mutex_unlock(&msc->error_irq_lock); >> + >>               mpam_reprogram_msc(msc); >> +        } >>       } >>   > > I don't understand how this happened that MPAMF_ECR gets lost, but msc->error_irq_hw_enabled > is kept as true. mpam_disable_msc_ecr() is triggered in __mpam_irq_handler() or mpam_unregister_irqs(). > Both are related to mpam_broken_work, which is invoked to disable the driver completely. > I don't see how MPAMF_ECR is cleared at CPU offline time. The reasoning is the same as to why mpam_reprogram_msc() is already run here. When all the CPUs affine to an MSC at a cache are offline then the cache instance and so the MSC might be switched off and lose register state. Hence, any registers we rely on need to set when the MSC comes back online. For PSCI_CPU_SUSPEND this needs to be handled by the firmware and for PSCI_CPU_OFF the driver handles it. Does that make any more sense? Thanks, Ben > >>       if (mpam_resctrl_enabled) > > Thanks, > Gavin >