From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from relay9-d.mail.gandi.net (relay9-d.mail.gandi.net [217.70.183.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF6441E4AE for ; Wed, 30 Oct 2024 12:39:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.199 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730291967; cv=none; b=tEbw38VGK6Zht/QG4J+JdP0RDPQyEWDUERs0Q4ItSNNscvo0mj2iBrFV7zlbGjhIo7JFXx9FDBqwFKrUzttFOFZdMK1d2Fjv9DX04qugHKahgPI4aYWxd7FC6K6uTZ2VaNngrLAiItwZ6XbO6MYG3PnMraqmoudCY+oY2Omm5Eo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730291967; c=relaxed/simple; bh=evsbQuE5KlminpWigsLOo6kybKyr+k0GSUf5MvO+Trs=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=nKR63HAYuIxrWcsgXdo9MAFQJLPHxV/CTr0YTHlqx5qwVY+7763YDv/eEv2C9r9W+67BWvhVBSgI8nV8t59udatqn6drpSN6quAgsWGymJryVbxAJg6dN3Ffq/CtkRiszBVISCZSGfonANNM64aVln28rxthTukTGkXcFhtw/Vc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=bcAFvYMC; arc=none smtp.client-ip=217.70.183.199 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="bcAFvYMC" Received: by mail.gandi.net (Postfix) with ESMTPSA id AAD87FF807; Wed, 30 Oct 2024 12:39:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730291963; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RhyPbAq58zDiCBw+D6bNpgM3r5/2NHM3HBjd+pUlFJA=; b=bcAFvYMCOgJmIyfQ6Od4D2NGh+yjgIYJBJxQUg3qQ+o60UW1DOpKVDktiyak3n+VQmdnsa EJVpA5uzPUgwZ/aiFVUuPY5y568dqlVkwqY4MND5o9cSwedrlU4yZBBeiy2VzqXnxSd15L pYNcEs7l8n7rOxbLUHeIM6ZfHwPwn8igcGwixykhVoxiYeeBLSTzanW+379WNS5zIhXq3k xXiou0bBC7aVj/1q85EW1Yhacm5WyLlHhaosYG9CmkclLmr6Sd3i4LKiRTh1z0kozvMEsA lKJ3MVYa+bpSUoJZkkxLdBPUfrQ5V3XE4CqDYgk3/EHjeCSmGwvGH2BkWKljtQ== Message-ID: Date: Wed, 30 Oct 2024 13:39:22 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/5] Implement setup_inteface() in the DaVinci NAND controller To: Krzysztof Kozlowski , Santosh Shilimkar , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi References: <20241030104717.88688-1-bastien.curutchet@bootlin.com> Content-Language: en-US From: Bastien Curutchet In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-GND-Sasl: bastien.curutchet@bootlin.com Hi Krzysztof, On 10/30/24 12:17 PM, Krzysztof Kozlowski wrote: > On 30/10/2024 11:47, Bastien Curutchet wrote: >> Hi all, >> >> This patch series aims to implement the setup_interface() operation in >> the DaVinci NAND controller to enable the use of all ONFI modes and >> improve the NAND access speed. >> > > Your changelog is supposed to explain also merging dependencies. Within > patchset or external. I'm not sure I understand what you mean here. Do you mean that I need to explicitly state that the patches in the drivers/mtd/nand/raw/davinci_nand.c depend on the ones in drivers/memory/ti-aemif.c ? There isn't any external dependency on this patch series. The ONFI modes are already managed by the NAND core driver (in drivers/mtd/nand/raw/nand_base.c). If a NAND controller wants to benefit from all the ONFI modes, it needs to implement the setup_interface() operation; otherwise it can only use the mode 0 which is the slowest. > >> This NAND controller is present in the DaVinci (OMAP L138) and Keystone2 >> SoCs and functions as a 'child' of the AEMIF controller. So its timings >> are set by the AEMIF controller itself from device-tree properties. >> Implementing the setup_interface() callback implies being able to update >> dynamically these timings, so the first two patches of the series modify >> the AEMIF driver to provide its 'children' a way to modify their chip >> select timing configuration. To do so, I add a ti-aemif.h header, I'm not >> sure whether this header should be located in include/memory or in >> include/linux/memory. I put it in include/memory because the folder >> already exists while include/linux/memory doesn't. > > All Linux headers go to include/linux/, so this one should as well. > Ok thank you, I'll move it there in V2. Best regards, Bastien