From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88E042701C1; Thu, 24 Apr 2025 15:05:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745507128; cv=none; b=YNed1wQUxbFy4MYyJArjfss69djIlCIAu2vkq61pEF/LQqzmAoOkRLjyaHL1B+fVCl2cNXaZ2QCaKMFRYY7Uq5kvjXd4sZJHbY+7bMtDjgHzJG6qUY4ocbZR0tgNT2DZDT67HrzuqdT1MOGbDLfddpLs9EYJklSueE4xTzvBCNg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745507128; c=relaxed/simple; bh=DZadV4dYY/zC+SdX3Ciq88DCbQxa2Avy7+9rB/BkoX0=; h=Message-ID:Date:MIME-Version:Subject:To:CC:References:From: In-Reply-To:Content-Type; b=MgAgUIeqzR8MVBKcpLxYXzcgwuBhfoIBeB3XxfoyNYhBw8R0xvonUanCpOljlUGio5Er/0wRnJm93ntd4DjtoerXdcixSAAYyXRmJXVys6kAsRCE8bvpXTjrIFiPZaFn0Z6l0ZCCZCMX3vVtYHAJIVgAZ1b1e5BPFO0RvsNkFNg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=bGNZrkbg; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="bGNZrkbg" Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 53OBPMk1019163; Thu, 24 Apr 2025 17:04:24 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= EbzdNbMuPcQgyg/32v679V2kcITSnqgFdSJKF+onCu4=; b=bGNZrkbgM7hP0A4d 0huWCtfENxlTtZ2hD9QWgmb98DIFXK5fBmBupMzY6axYs0FrA/0LWmfz0WhsStka AUXFj0pYsKuCM2wNw3Noz8aYCKXGStw8mUCIHn1PU8SS3MuLYegugGWwOdnCglQS so57zD+/Q1kPH+lUcNiN2fR6/+s7xU5O1AjiWYlDUID34TOZerwOJJCOsxm/73wD AKWfN54uWLHEgaWECt+7UHmgOfzc5a9lH3nXnAz3hT37RZh9W27f0QUDHzBg/F3h 2H+eskpgY2tz9SOoLS7XLLDm437GAqrqDrmqZ4wiJvlEm8NsT0+VsUGPYke1l5R3 kW1R0Q== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 466jjvg1q7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 24 Apr 2025 17:04:21 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 7BB1040046; Thu, 24 Apr 2025 17:01:47 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id A4E6D9C40B5; Thu, 24 Apr 2025 16:59:49 +0200 (CEST) Received: from [10.48.86.196] (10.48.86.196) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 24 Apr 2025 16:59:48 +0200 Message-ID: Date: Thu, 24 Apr 2025 16:59:47 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [Linux-stm32] [PATCH 03/12] pinctrl: stmfx: use new GPIO line value setter callbacks To: Bartosz Golaszewski , Basavaraj Natikar , Shyam Sundar S K , Linus Walleij , Chen-Yu Tsai , Maxime Coquelin , Alexandre Torgue , =?UTF-8?Q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam , Paul Cercueil , Steen Hegelund , Daniel Machon , , Ludovic Desroches , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Krzysztof Kozlowski , Sylwester Nawrocki , Alim Akhtar CC: , Bartosz Golaszewski , , , , , , References: <20250424-gpiochip-set-rv-pinctrl-part2-v1-0-504f91120b99@linaro.org> <20250424-gpiochip-set-rv-pinctrl-part2-v1-3-504f91120b99@linaro.org> Content-Language: en-US From: Amelie Delaunay In-Reply-To: <20250424-gpiochip-set-rv-pinctrl-part2-v1-3-504f91120b99@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-24_06,2025-04-24_01,2025-02-21_01 On 4/24/25 10:35, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski > > struct gpio_chip now has callbacks for setting line values that return > an integer, allowing to indicate failures. Convert the driver to using > them. > > Signed-off-by: Bartosz Golaszewski Reviewed-by: Amelie Delaunay > --- > drivers/pinctrl/pinctrl-stmfx.c | 13 ++++++++----- > 1 file changed, 8 insertions(+), 5 deletions(-) > > diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c > index aae01120dc52..f4fdcaa043e6 100644 > --- a/drivers/pinctrl/pinctrl-stmfx.c > +++ b/drivers/pinctrl/pinctrl-stmfx.c > @@ -115,14 +115,14 @@ static int stmfx_gpio_get(struct gpio_chip *gc, unsigned int offset) > return ret ? ret : !!(value & mask); > } > > -static void stmfx_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) > +static int stmfx_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) > { > struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); > u32 reg = value ? STMFX_REG_GPO_SET : STMFX_REG_GPO_CLR; > u32 mask = get_mask(offset); > > - regmap_write_bits(pctl->stmfx->map, reg + get_reg(offset), > - mask, mask); > + return regmap_write_bits(pctl->stmfx->map, reg + get_reg(offset), > + mask, mask); > } > > static int stmfx_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) > @@ -161,8 +161,11 @@ static int stmfx_gpio_direction_output(struct gpio_chip *gc, > struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); > u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset); > u32 mask = get_mask(offset); > + int ret; > > - stmfx_gpio_set(gc, offset, value); > + ret = stmfx_gpio_set(gc, offset, value); > + if (ret) > + return ret; > > return regmap_write_bits(pctl->stmfx->map, reg, mask, mask); > } > @@ -694,7 +697,7 @@ static int stmfx_pinctrl_probe(struct platform_device *pdev) > pctl->gpio_chip.direction_input = stmfx_gpio_direction_input; > pctl->gpio_chip.direction_output = stmfx_gpio_direction_output; > pctl->gpio_chip.get = stmfx_gpio_get; > - pctl->gpio_chip.set = stmfx_gpio_set; > + pctl->gpio_chip.set_rv = stmfx_gpio_set; > pctl->gpio_chip.set_config = gpiochip_generic_config; > pctl->gpio_chip.base = -1; > pctl->gpio_chip.ngpio = pctl->pctl_desc.npins; >