From: James Clark <james.clark@linaro.org>
To: Ian Rogers <irogers@google.com>
Cc: Yangyu Chen <cyy@cyyself.name>,
Namhyung Kim <namhyung@kernel.org>,
linux-perf-users@vger.kernel.org,
John Garry <john.g.garry@oracle.com>,
Will Deacon <will@kernel.org>, Mike Leach <mike.leach@linaro.org>,
Leo Yan <leo.yan@linux.dev>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>,
Adrian Hunter <adrian.hunter@intel.com>,
Liang Kan <kan.liang@linux.intel.com>,
Yoshihiro Furudera <fj5100bi@fujitsu.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 0/2] perf vendor events arm64: Add A720/A520 events/metrics
Date: Tue, 18 Feb 2025 09:30:23 +0000 [thread overview]
Message-ID: <fe46069e-c52e-45ee-b4b3-8b929fb83b31@linaro.org> (raw)
In-Reply-To: <CAP-5=fVAhLLH-a0_wLo8dPoMLOb6rOJiTgGh-OFZJJoaLFE-8Q@mail.gmail.com>
On 18/02/2025 12:41 am, Ian Rogers wrote:
> On Fri, Feb 14, 2025 at 2:02 AM James Clark <james.clark@linaro.org> wrote:
>>
>>
>>
>> On 14/02/2025 5:49 am, Yangyu Chen wrote:
>>>
>>>
>>>> On 14 Feb 2025, at 09:12, Namhyung Kim <namhyung@kernel.org> wrote:
>>>>
>>>> Hello,
>>>>
>>>> On Thu, Feb 13, 2025 at 11:11:01PM +0800, Yangyu Chen wrote:
>>>>> This patchset adds the perf JSON files for the Cortex-A720 and Cortex-A520
>>>>> processors. Some events have been tested on Raxda Orion 6 with Cix P1 SoC
>>>>> (8xA720 + 4xA520) running mainline Kernel with ACPI mode.
>>>>
>>>> I'm curious how the name of PMUs look like. It is cortex_a720 (or a520)?
>>>
>>> The name of PMUs comes from Arm's documentation. I have included these
>>> links in each patch.
>>>
>>>> I remember there's a logic to check the length of hex digits at the end.
>>>>
>>>
>>> Could you provide more details about this?
>>>
>>>> Ian, are you ok with this?
>>>>
>>
>> I think they wouldn't be merged because they're core PMUs, so should be
>> fine? Even though they would otherwise be merged because they're more
>> than 3 hex digits.
>
> Do we know the PMU names? If they are cortex_a520 and cortex_a720 then
It will be "armv9_cortex_a720" from this line:
PMUV3_INIT_SIMPLE(armv9_cortex_a720)
> this comment at least reads a little stale:
> https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/util/pmus.c?h=perf-tools-next#n76
> ```
> /*
> * There is a '_{num}' suffix. For decimal suffixes any length
> * will do, for hexadecimal ensure more than 2 hex digits so
> * that S390's cpum_cf PMU doesn't match.
> */
> ```
> James is right that core PMUs aren't put on the same list as uncore/other PMUs.
>
> Thanks,
> Ian
>
>>>> Thanks,
>>>> Namhyung
>>>>
>>>>>
>>>>> Yangyu Chen (2):
>>>>> perf vendor events arm64: Add Cortex-A720 events/metrics
>>>>> perf vendor events arm64: Add Cortex-A520 events/metrics
>>>>>
>>>>> .../arch/arm64/arm/cortex-a520/bus.json | 26 ++
>>>>> .../arch/arm64/arm/cortex-a520/exception.json | 18 +
>>>>> .../arm64/arm/cortex-a520/fp_operation.json | 14 +
>>>>> .../arch/arm64/arm/cortex-a520/general.json | 6 +
>>>>> .../arch/arm64/arm/cortex-a520/l1d_cache.json | 50 ++
>>>>> .../arch/arm64/arm/cortex-a520/l1i_cache.json | 14 +
>>>>> .../arch/arm64/arm/cortex-a520/l2_cache.json | 46 ++
>>>>> .../arch/arm64/arm/cortex-a520/l3_cache.json | 21 +
>>>>> .../arch/arm64/arm/cortex-a520/ll_cache.json | 10 +
>>>>> .../arch/arm64/arm/cortex-a520/memory.json | 58 +++
>>>>> .../arch/arm64/arm/cortex-a520/metrics.json | 373 +++++++++++++++
>>>>> .../arch/arm64/arm/cortex-a520/pmu.json | 8 +
>>>>> .../arch/arm64/arm/cortex-a520/retired.json | 90 ++++
>>>>> .../arm64/arm/cortex-a520/spec_operation.json | 70 +++
>>>>> .../arch/arm64/arm/cortex-a520/stall.json | 82 ++++
>>>>> .../arch/arm64/arm/cortex-a520/sve.json | 22 +
>>>>> .../arch/arm64/arm/cortex-a520/tlb.json | 78 ++++
>>>>> .../arch/arm64/arm/cortex-a520/trace.json | 32 ++
>>>>> .../arch/arm64/arm/cortex-a720/bus.json | 18 +
>>>>> .../arch/arm64/arm/cortex-a720/exception.json | 62 +++
>>>>> .../arm64/arm/cortex-a720/fp_operation.json | 22 +
>>>>> .../arch/arm64/arm/cortex-a720/general.json | 10 +
>>>>> .../arch/arm64/arm/cortex-a720/l1d_cache.json | 50 ++
>>>>> .../arch/arm64/arm/cortex-a720/l1i_cache.json | 14 +
>>>>> .../arch/arm64/arm/cortex-a720/l2_cache.json | 62 +++
>>>>> .../arch/arm64/arm/cortex-a720/l3_cache.json | 22 +
>>>>> .../arch/arm64/arm/cortex-a720/ll_cache.json | 10 +
>>>>> .../arch/arm64/arm/cortex-a720/memory.json | 54 +++
>>>>> .../arch/arm64/arm/cortex-a720/metrics.json | 436 ++++++++++++++++++
>>>>> .../arch/arm64/arm/cortex-a720/pmu.json | 8 +
>>>>> .../arch/arm64/arm/cortex-a720/retired.json | 90 ++++
>>>>> .../arch/arm64/arm/cortex-a720/spe.json | 42 ++
>>>>> .../arm64/arm/cortex-a720/spec_operation.json | 90 ++++
>>>>> .../arch/arm64/arm/cortex-a720/stall.json | 82 ++++
>>>>> .../arch/arm64/arm/cortex-a720/sve.json | 50 ++
>>>>> .../arch/arm64/arm/cortex-a720/tlb.json | 74 +++
>>>>> .../arch/arm64/arm/cortex-a720/trace.json | 32 ++
>>>>> .../arch/arm64/common-and-microarch.json | 15 +
>>>>> tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +
>>>>> 39 files changed, 2263 insertions(+)
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/bus.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/exception.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/fp_operation.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/general.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l1d_cache.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l1i_cache.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l2_cache.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l3_cache.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/ll_cache.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/memory.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/metrics.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/pmu.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/retired.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/spec_operation.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/stall.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/sve.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/tlb.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/trace.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/bus.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/exception.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/fp_operation.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/general.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l1d_cache.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l1i_cache.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l2_cache.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l3_cache.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/ll_cache.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/memory.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/metrics.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/pmu.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/retired.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/spe.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/spec_operation.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/stall.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/sve.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/tlb.json
>>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/trace.json
>>>>>
>>>>> --
>>>>> 2.47.2
>>>>>
>>>
>>
next prev parent reply other threads:[~2025-02-18 9:30 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-13 15:11 Yangyu Chen
2025-02-13 15:12 ` [PATCH 1/2] perf vendor events arm64: Add Cortex-A720 events/metrics Yangyu Chen
2025-02-13 16:49 ` Ian Rogers
2025-02-13 15:12 ` [PATCH 2/2] perf vendor events arm64: Add Cortex-A520 events/metrics Yangyu Chen
2025-02-13 16:53 ` Ian Rogers
2025-02-14 1:12 ` [PATCH 0/2] perf vendor events arm64: Add A720/A520 events/metrics Namhyung Kim
2025-02-14 5:49 ` Yangyu Chen
2025-02-14 10:02 ` James Clark
2025-02-18 0:41 ` Ian Rogers
2025-02-18 9:30 ` James Clark [this message]
2025-02-18 22:19 ` Namhyung Kim
2025-02-18 22:33 ` Ian Rogers
2025-02-19 15:25 ` James Clark
2025-02-19 18:37 ` Ian Rogers
2025-02-20 3:37 ` Yangyu Chen
[not found] ` <tencent_EDA4AFD185EF51104EDBCEB109D720862B05@qq.com>
2025-02-20 14:37 ` James Clark
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