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[212.182.62.129]) by smtp.gmail.com with ESMTPSA id bf14-20020a0564021a4e00b005362bcc089csm10152630edb.67.2023.10.12.09.59.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Oct 2023 09:59:52 -0700 (PDT) Message-ID: Date: Thu, 12 Oct 2023 18:59:48 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 1/3] arm64: dts: qcom: Add interconnect nodes for SDX75 Content-Language: en-US To: Rohit Agarwal , agross@kernel.org, andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, dmitry.baryshkov@linaro.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <1696406908-9688-1-git-send-email-quic_rohiagar@quicinc.com> <1696406908-9688-2-git-send-email-quic_rohiagar@quicinc.com> <3a042a26-81b4-4ab3-ba03-a38ae876634b@linaro.org> <6da8dc86-0b9a-488f-9046-9d9d269beeaf@quicinc.com> From: Konrad Dybcio In-Reply-To: <6da8dc86-0b9a-488f-9046-9d9d269beeaf@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/12/23 18:57, Rohit Agarwal wrote: > > On 10/12/2023 10:18 PM, Konrad Dybcio wrote: >> >> >> On 10/4/23 10:08, Rohit Agarwal wrote: >>> Add interconnect nodes to support interconnects on SDX75. >>> Also parallely add the interconnect property for UART required >>> so that the bootup to shell does not break with interconnects >>> in place. >>> >>> Signed-off-by: Rohit Agarwal >>> --- >>>   arch/arm64/boot/dts/qcom/sdx75.dtsi | 52 >>> +++++++++++++++++++++++++++++++++++++ >>>   1 file changed, 52 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi >>> b/arch/arm64/boot/dts/qcom/sdx75.dtsi >>> index e180aa4..b4723fa 100644 >>> --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi >>> @@ -8,6 +8,8 @@ >>>     #include >>>   #include >>> +#include >>> +#include >>>   #include >>>   #include >>>   #include >>> @@ -203,6 +205,19 @@ >>>           }; >>>       }; >>>   +    clk_virt: interconnect-0 { >>> +        compatible = "qcom,sdx75-clk-virt"; >>> +        #interconnect-cells = <2>; >>> +        qcom,bcm-voters = <&apps_bcm_voter>; >>> +        clocks = <&rpmhcc RPMH_QPIC_CLK>; >>> +    }; >>> + >>> +    mc_virt: interconnect-1 { >>> +        compatible = "qcom,sdx75-mc-virt"; >>> +        #interconnect-cells = <2>; >>> +        qcom,bcm-voters = <&apps_bcm_voter>; >>> +    }; >>> + >>>       memory@80000000 { >>>           device_type = "memory"; >>>           reg = <0x0 0x80000000 0x0 0x0>; >>> @@ -434,6 +449,9 @@ >>>               clock-names = "m-ahb", >>>                         "s-ahb"; >>>               iommus = <&apps_smmu 0xe3 0x0>; >>> +            interconnects = <&clk_virt MASTER_QUP_CORE_0 >>> QCOM_ICC_TAG_ALWAYS >>> +                     &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>; >>> +            interconnect-names = "qup-core"; >> No qup-config? >> >> My brain compiler says this would cause a dt checker warning, at least >> on next-20231012. > If I check the tip, then there is only one interconnect entry. > https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/soc/qcom/qcom%2Cgeni-se.yaml#L50 > For the debug uart, the qup-config is added. > I did check the dtbs_check before sending these patches. > Please let me know if I am missing anything. Oh, my brain compiler was correct, but for the wrong input data :) I thought you added this property to the UART itself, not to the QUP controller. Yes, you're right. Konrad