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Miller" , Jakub Kicinski , Paolo Abeni , Simon Horman , Russell King , Andrew Lunn , Heiner Kallweit , Eric Dumazet , Lee Jones , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, mfd@lists.linux.dev, Martin Kaistra , Benedikt Spranger Date: Fri, 13 Nov 2026 20:07:41 +0100 In-Reply-To: <20261112-unselfish-congenial-waxbill-c7f9e3@quoll> References: <20261105-devel-vstrassheim-soce-dsa-ml-v4-0-02f3cde2afa1@linutronix.de> <20261105-devel-vstrassheim-soce-dsa-ml-v4-3-02f3cde2afa1@linutronix.de> <20261112-unselfish-congenial-waxbill-c7f9e3@quoll> Organization: Linutronix GmbH Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 On Thu, 2026-11-12 at 11:33 +0100, Krzysztof Kozlowski wrote: > On Thu, Nov 05, 2026 at 03:16:47PM +0100, Vasilij Strassheim wrote: > > Add a binding for the Ethernet switch function integrated into SoC-e > > SWIP cores. > >=20 > > Signed-off-by: Vasilij Strassheim > > --- > > .../bindings/net/dsa/soce,swip-switch.yaml | 96 ++++++++++++++= ++++++++ > > 1 file changed, 96 insertions(+) > >=20 > > diff --git a/Documentation/devicetree/bindings/net/dsa/soce,swip-switch= .yaml b/Documentation/devicetree/bindings/net/dsa/soce,swip-switch.yaml > > new file mode 100644 > > index 000000000000..daac779c466d > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/net/dsa/soce,swip-switch.yaml > > @@ -0,0 +1,96 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/net/dsa/soce,swip-switch.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: SoC-e SWIP FPGA Ethernet switch function > > + > > +maintainers: > > + - Vasilij Strassheim > > + > > +description: > > + Ethernet switch function of the SoC-e Switch IP (SWIP) FPGA core. Th= e port > > + count and presence of VLAN and STP register blocks depend on the FPG= A > > + synthesis configuration. > > + > > +$ref: dsa.yaml#/$defs/ethernet-ports > > + > > +properties: > > + compatible: > > + const: soce,swip-switch-00-04-0c-10 > > + description: > > + This compatible identifies the register layout; its suffix gives > > + the offsets of the core version and feature identification > > + registers (0x00, 0x04, 0x0c, and 0x10). Port counts and optional > > + features depend on the FPGA synthesis configuration and are > > + detected at runtime using this register layout. > > + > > + reg: false > > + > > + reg-names: false >=20 > I don't get why do you need these two above? They are redundant here. I will remove/fix them as part of the binding update once we have agreed on whether to keep the MFD model. >=20 > > + > > + ethernet-ports: > > + type: object > > + patternProperties: > > + '^ethernet-port@[0-9a-f]+$': > > + type: object > > + > > + properties: > > + reg: > > + maximum: 30 > > + description: Switch port index, from 0 through 30. > > + > > + phy-mode: > > + enum: > > + - mii > > + - gmii > > + - rmii > > + - rgmii > > + - rgmii-id > > + - rgmii-rxid > > + - rgmii-txid > > + > > + required: > > + - reg > > + - phy-mode >=20 > Best regards, > Krzysztof >=20 Thanks, Vasilij pw-bot: changes-requested