From: Mario Limonciello <superm1@kernel.org>
To: "Gautham R. Shenoy" <gautham.shenoy@amd.com>
Cc: Perry Yuan <perry.yuan@amd.com>,
Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>,
"open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)"
<linux-kernel@vger.kernel.org>,
"open list:CPU FREQUENCY SCALING FRAMEWORK"
<linux-pm@vger.kernel.org>,
Mario Limonciello <mario.limonciello@amd.com>
Subject: Re: [PATCH v3 17/18] cpufreq/amd-pstate: Rework CPPC enabling
Date: Wed, 19 Feb 2025 12:05:57 -0600 [thread overview]
Message-ID: <fe9b5d8d-5cbb-4d0c-bd12-b15a8d44062d@kernel.org> (raw)
In-Reply-To: <Z7X4BfEAbRwCg2Dg@BLRRASHENOY1.amd.com>
On 2/19/2025 09:25, Gautham R. Shenoy wrote:
> On Mon, Feb 17, 2025 at 04:07:06PM -0600, Mario Limonciello wrote:
>> From: Mario Limonciello <mario.limonciello@amd.com>
>>
>> The CPPC enable register is configured as "write once". That is
>> any future writes don't actually do anything.
>>
>> Because of this, all the cleanup paths that currently exist for
>> CPPC disable are non-effective.
>>
>> Rework CPPC enable to only enable after all the CAP registers have
>> been read to avoid enabling CPPC on CPUs with invalid _CPC or
>> unpopulated MSRs.
>>
>> As the register is write once, remove all cleanup paths as well.
>>
>> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
>> ---
>> v3:
>> * Fixup for suspend/resume issue
>> ---
> [..snip..]
>
>>
>> -static int shmem_cppc_enable(bool enable)
>> +static int shmem_cppc_enable(struct cpufreq_policy *policy)
>> {
>> - int cpu, ret = 0;
>> + struct amd_cpudata *cpudata = policy->driver_data;
>> struct cppc_perf_ctrls perf_ctrls;
>> + int ret;
>>
>> - if (enable == cppc_enabled)
>> - return 0;
>> + ret = cppc_set_enable(cpudata->cpu, 1);
>> + if (ret)
>> + return ret;
>>
>> - for_each_present_cpu(cpu) {
>> - ret = cppc_set_enable(cpu, enable);
>> + /* Enable autonomous mode for EPP */
>> + if (cppc_state == AMD_PSTATE_ACTIVE) {
>> + /* Set desired perf as zero to allow EPP firmware control */
>> + perf_ctrls.desired_perf = 0;
>> + ret = cppc_set_perf(cpudata->cpu, &perf_ctrls);
>> if (ret)
>> return ret;
>
> We don't need the if condition here. There is nothing following this
> inside the if block and the function return "ret" soon after coming
> out of this if block.
>
>
>> -
>> - /* Enable autonomous mode for EPP */
>> - if (cppc_state == AMD_PSTATE_ACTIVE) {
>> - /* Set desired perf as zero to allow EPP firmware control */
>> - perf_ctrls.desired_perf = 0;
>> - ret = cppc_set_perf(cpu, &perf_ctrls);
>> - if (ret)
>> - return ret;
>> - }
>> }
>>
>> - cppc_enabled = enable;
>> return ret;
>> }
>>
>> DEFINE_STATIC_CALL(amd_pstate_cppc_enable, msr_cppc_enable);
>>
>> -static inline int amd_pstate_cppc_enable(bool enable)
> [..snip..]
>
>>
>> -static int amd_pstate_epp_reenable(struct cpufreq_policy *policy)
>> +static int amd_pstate_epp_cpu_online(struct cpufreq_policy *policy)
>> {
>> struct amd_cpudata *cpudata = policy->driver_data;
>> union perf_cached perf = READ_ONCE(cpudata->perf);
>> int ret;
>>
>> - ret = amd_pstate_cppc_enable(true);
>> - if (ret)
>> - pr_err("failed to enable amd pstate during resume, return %d\n", ret);
>> -
>> -
>> - return amd_pstate_epp_update_limit(policy);
>> -}
>> + pr_debug("AMD CPU Core %d going online\n", cpudata->cpu);
>>
>> -static int amd_pstate_epp_cpu_online(struct cpufreq_policy *policy)
>> -{
>> - struct amd_cpudata *cpudata = policy->driver_data;
>> - int ret;
>> + ret = amd_pstate_cppc_enable(policy);
>> + if (ret)
>> + return ret;
>>
>> - pr_debug("AMD CPU Core %d going online\n", cpudata->cpu);
>>
>> - ret = amd_pstate_epp_reenable(policy);
>> + ret = amd_pstate_update_perf(policy, 0, 0, perf.highest_perf, cpudata->epp_cached, false);
>
> Previously, when a CPU came online, the callpath would be
> amd_pstate_epp_cpu_online(policy)
> --> amd_pstate_epp_reenable(policy)
> --> amd_pstate_epp_update_limit(policy)
> --> amd_pstate_epp_update_limit(policy)
>
> which reevaluates the min_perf_limit and max_perf_limit based on
> policy->min and policy->max and then calls
>
> amd_pstate_update_perf(policy, min_limit_perf, 0, max_limit_perf, epp, false)
>
> With this patch, we call
>
> amd_pstate_update_perf(policy, 0, 0, perf.highest_perf, cpudata->epp_cached, false);
>
> which would set CPPC.min_perf to 0.
>
> I guess this should be ok since cpufreq_online() would eventually call
> amd_pstate_verify() and amd_pstate_epp_set_policy() which should
> re-initialize the the min_limit_perf and max_limit_perf. Though I
> haven't verified if the behaviour changes with this patch when the CPU
> is offlined and brought back online.
I'll double check with removing amd_pstate_update_perf() call from
amd_pstate_epp_cpu_online(). I think it will be clearer to let it get
set from the amd_pstate_epp_set_policy() call.
next prev parent reply other threads:[~2025-02-19 18:05 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-17 22:06 [PATCH v3 00/18] amd-pstate cleanups Mario Limonciello
2025-02-17 22:06 ` [PATCH v3 01/18] cpufreq/amd-pstate: Invalidate cppc_req_cached during suspend Mario Limonciello
2025-02-19 5:24 ` Gautham R. Shenoy
2025-02-19 17:21 ` Mario Limonciello
2025-02-19 6:12 ` Dhananjay Ugwekar
2025-02-19 6:37 ` Dhananjay Ugwekar
2025-02-17 22:06 ` [PATCH v3 02/18] cpufreq/amd-pstate: Show a warning when a CPU fails to setup Mario Limonciello
2025-02-19 6:14 ` Dhananjay Ugwekar
2025-02-17 22:06 ` [PATCH v3 03/18] cpufreq/amd-pstate: Drop min and max cached frequencies Mario Limonciello
2025-02-19 5:25 ` Gautham R. Shenoy
2025-02-19 8:00 ` Dhananjay Ugwekar
2025-02-19 17:29 ` Mario Limonciello
2025-02-17 22:06 ` [PATCH v3 04/18] cpufreq/amd-pstate: Move perf values into a union Mario Limonciello
2025-02-19 10:57 ` Dhananjay Ugwekar
2025-02-25 0:29 ` Mario Limonciello
2025-02-25 4:28 ` Dhananjay Ugwekar
2025-02-17 22:06 ` [PATCH v3 05/18] cpufreq/amd-pstate: Overhaul locking Mario Limonciello
2025-02-17 22:06 ` [PATCH v3 06/18] cpufreq/amd-pstate: Drop `cppc_cap1_cached` Mario Limonciello
2025-02-17 22:06 ` [PATCH v3 07/18] cpufreq/amd-pstate-ut: Use _free macro to free put policy Mario Limonciello
2025-02-17 22:06 ` [PATCH v3 08/18] cpufreq/amd-pstate-ut: Allow lowest nonlinear and lowest to be the same Mario Limonciello
2025-02-17 22:06 ` [PATCH v3 09/18] cpufreq/amd-pstate-ut: Drop SUCCESS and FAIL enums Mario Limonciello
2025-02-17 22:06 ` [PATCH v3 10/18] cpufreq/amd-pstate-ut: Run on all of the correct CPUs Mario Limonciello
2025-02-19 5:26 ` Gautham R. Shenoy
2025-02-17 22:07 ` [PATCH v3 11/18] cpufreq/amd-pstate-ut: Adjust variable scope for amd_pstate_ut_check_freq() Mario Limonciello
2025-02-24 6:12 ` Dhananjay Ugwekar
2025-02-17 22:07 ` [PATCH v3 12/18] cpufreq/amd-pstate: Replace all AMD_CPPC_* macros with masks Mario Limonciello
2025-02-17 22:07 ` [PATCH v3 13/18] cpufreq/amd-pstate: Cache CPPC request in shared mem case too Mario Limonciello
2025-02-17 22:07 ` [PATCH v3 14/18] cpufreq/amd-pstate: Move all EPP tracing into *_update_perf and *_set_epp functions Mario Limonciello
2025-02-17 22:07 ` [PATCH v3 15/18] cpufreq/amd-pstate: Update cppc_req_cached for shared mem EPP writes Mario Limonciello
2025-02-17 22:07 ` [PATCH v3 16/18] cpufreq/amd-pstate: Drop debug statements for policy setting Mario Limonciello
2025-02-17 22:07 ` [PATCH v3 17/18] cpufreq/amd-pstate: Rework CPPC enabling Mario Limonciello
2025-02-19 15:25 ` Gautham R. Shenoy
2025-02-19 18:05 ` Mario Limonciello [this message]
2025-02-17 22:07 ` [PATCH v3 18/18] cpufreq/amd-pstate: Stop caching EPP Mario Limonciello
2025-02-19 15:41 ` Gautham R. Shenoy
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