From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933213AbcHaLMW (ORCPT ); Wed, 31 Aug 2016 07:12:22 -0400 Received: from mx1.redhat.com ([209.132.183.28]:33778 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758851AbcHaLMS (ORCPT ); Wed, 31 Aug 2016 07:12:18 -0400 Subject: Re: RFC: Petition Intel/AMD to add POPF_IF insn To: Paolo Bonzini , Linus Torvalds References: <8de26c33-5597-bf00-2ac5-d265ba01d0d4@redhat.com> <1686aa11-152d-9416-34dd-17820de7a7b6@redhat.com> Cc: Andy Lutomirski , Sara Sharon , Dan Williams , =?UTF-8?Q?Christian_K=c3=b6nig?= , Vinod Koul , Alex Deucher , Johannes Berg , "Rafael J. Wysocki" , Andy Lutomirski , the arch/x86 maintainers , Ingo Molnar , LKML , Adrian Hunter From: Denys Vlasenko Message-ID: Date: Wed, 31 Aug 2016 13:12:00 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Wed, 31 Aug 2016 11:12:05 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 08/19/2016 12:54 PM, Paolo Bonzini wrote: > On 18/08/2016 19:24, Linus Torvalds wrote: >>>> I didn't do CPL0 tests yet. Realized that cli/sti can be tested in userspace >>>> if we set iopl(3) first. >> Yes, but it might not be the same. So the timings could be very >> different from a cpl0 case. > > FWIW I recently measured around 20 cycles for a popf as well on > Haswell-EP and CPL=0 (that was for commit f2485b3e0c6c, "KVM: x86: use > guest_exit_irqoff", 2016-07-01). Thanks for confirmation. I revisited benchmarking of the if (flags & X86_EFLAGS_IF) native_irq_enable(); patch. In "make -j20" kernel compiles on a 8-way (HT) CPU, it shows some ~5 second improvement during ~16 minute compile. That's 0.5% speedup. It's ok, but not something to bee too excited. 80 e6 02 and $0x2,%dh 74 01 je ffffffff810101ae fb sti 41 f6 86 91 00 00 00 02 testb $0x2,0x91(%r14) 74 01 je ffffffff81013ce7 fb sti f6 83 91 00 00 00 02 testb $0x2,0x91(%rbx) 74 01 je ffffffff81013efa fb sti 41 f7 c4 00 02 00 00 test $0x200,%r12d 74 01 je ffffffff8101615d fb sti Here we trade 20-cycle POPF for either 4-cycle STI, or a branch (which is either ~1 cycle if predicted, or ~20 cycles if mispredicted). The disassembly of vmlinux shows that gcc generates these asm patterns: I still think a dedicated instruction for a conditional STI is worth asking for. Along the lines of "If bit 9 in the r/m argument is set, then STI, else nothing". What do people from CPU companies say?