From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6ECAC433FE for ; Wed, 15 Dec 2021 15:16:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243874AbhLOPQt (ORCPT ); Wed, 15 Dec 2021 10:16:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33164 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242637AbhLOPQr (ORCPT ); Wed, 15 Dec 2021 10:16:47 -0500 Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:e::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C00AC061574; Wed, 15 Dec 2021 07:16:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=MIME-Version:Content-Type:References: In-Reply-To:Date:Cc:To:From:Subject:Message-ID:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=B4tpyQga7SH+7JGSMwW7fY4N3Vkn2z/AXyXu7q+/GAg=; b=d2NhVMFQtnUHLgOY/a42pNO4zb jZP0ORdf1Xj0s9Glneacaa8TV/kjMf56Lu0mXSswtnnT12AKLh0n4NS287cCdgiQMc3ROlfLSPlo/ u/0Uy759pFo1hEUu5bhK83WECfAjU86QOcIrUOjbdxLxspvc4JK4EinB2FM+zaf/nIR4P1nGp/EAX uFVB6BD3NM3fZkQUlLxblvdKPN08v+WMsHAuMzVTD9H+VHveVEpKHqpdpXam3ABlsu1Mfq8UI4rs7 1xKw0mlTrSq4IM66F1gSnQz+/QsstTW8yOOyFvn4PEY1xO1UpB/xFfx8Ubjh+7Qib6ko08hXrqj+z ihHVFhoQ==; Received: from [2001:8b0:10b:1::3ae] (helo=u3832b3a9db3152.infradead.org) by bombadil.infradead.org with esmtpsa (Exim 4.94.2 #2 (Red Hat Linux)) id 1mxW15-001K2L-0I; Wed, 15 Dec 2021 15:16:27 +0000 Message-ID: Subject: Re: [PATCH v2 3/7] cpu/hotplug: Add dynamic parallel bringup states before CPUHP_BRINGUP_CPU From: David Woodhouse To: Mark Rutland Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H . Peter Anvin" , Paolo Bonzini , "Paul E . McKenney" , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, rcu@vger.kernel.org, mimoja@mimoja.de, hewenliang4@huawei.com, hushiyuan@huawei.com, luolongjun@huawei.com, hejingxian@huawei.com Date: Wed, 15 Dec 2021 15:16:22 +0000 In-Reply-To: References: <20211214123250.88230-1-dwmw2@infradead.org> <20211214123250.88230-4-dwmw2@infradead.org> Content-Type: multipart/signed; micalg="sha-256"; protocol="application/pkcs7-signature"; boundary="=-VjU8phqa4WulPKIa+BnH" User-Agent: Evolution 3.36.5-0ubuntu1 MIME-Version: 1.0 X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --=-VjU8phqa4WulPKIa+BnH Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, 2021-12-15 at 11:10 +0000, Mark Rutland wrote: > On Tue, Dec 14, 2021 at 08:32:29PM +0000, David Woodhouse wrote: > > On Tue, 2021-12-14 at 14:24 +0000, Mark Rutland wrote: > > > On Tue, Dec 14, 2021 at 12:32:46PM +0000, David Woodhouse wrote: > > > > From: David Woodhouse < > > > > dwmw@amazon.co.uk > > > >=20 > > > >=20 > > > > If the platform registers these states, bring all CPUs to each regi= stered > > > > state in turn, before the final bringup to CPUHP_BRINGUP_CPU. This = allows > > > > the architecture to parallelise the slow asynchronous tasks like se= nding > > > > INIT/SIPI and waiting for the AP to come to life. > > > >=20 > > > > There is a subtlety here: even with an empty CPUHP_BP_PARALLEL_DYN = step, > > > > this means that *all* CPUs are brought through the prepare states a= nd to > > > > CPUHP_BP_PREPARE_DYN before any of them are taken to CPUHP_BRINGUP_= CPU > > > > and then are allowed to run for themselves to CPUHP_ONLINE. > > > >=20 > > > > So any combination of prepare/start calls which depend on A-B order= ing > > > > for each CPU in turn, such as the X2APIC code which used to allocat= e a > > > > cluster mask 'just in case' and store it in a global variable in th= e > > > > prep stage, then potentially consume that preallocated structure fr= om > > > > the AP and set the global pointer to NULL to be reallocated in > > > > CPUHP_X2APIC_PREPARE for the next CPU... would explode horribly. > > > >=20 > > > > We believe that X2APIC was the only such case, for x86. But this is= why > > > > it remains an architecture opt-in. For now. > > >=20 > > > It might be worth elaborating with a non-x86 example, e.g. > > >=20 > > > > We believe that X2APIC was the only such case, for x86. Other arch= itectures > > > > have similar requirements with global variables used during bringu= p (e.g. > > > > `secondary_data` on arm/arm64), so architectures must opt-in for n= ow. > > >=20 > > > ... so that we have a specific example of how unconditionally enablin= g this for > > > all architectures would definitely break things today. > >=20 > > I do not have such an example, and I do not know that it would > > definitely break things to turn it on for all architectures today. > >=20 > > The x2apic one is an example of why it *might* break random > > architectures and thus why it needs to be an architecture opt-in. >=20 > Ah; I had thought we did the `secondary_data` setup in a PREPARE step, an= d > hence it was a comparable example, but I was mistaken. Sorry for the nois= e! >=20 Right, that's entirely within your __cpu_up(). You can stare at Thomas's patch for inspiration on how to cope with that one. In arch/arm64/kernel/smp.c you have a comment saying * as from 2.5, kernels no longer have an init_tasks structure * so we need some other way of telling a new secondary core * where to place its SVC stack In x86, the idle task pointer is in the per_cpu data. The real mode bringup now starts with the CPU's APICID (which it can get from CPUID), looks that up in the cpuid_to_apicid[] array to find the CPU#, then finds its own per_cpu data, and gets everything else it needs (including the initial stack) from there. > > > FWIW, that's something I would like to cleanup for arm64 for general > > > robustness, and if that would make it possible for us to have paralle= l bringup > > > in future that would be a nice bonus. > >=20 > > Yes. But although I lay the groundwork here, the arch can't *actually* > > do parallel bringup without some arch-specific work, so auditing the > > pre-bringup states is the easy part. :) >=20 > Sure; that was trying to be a combination of: >=20 > * This looks nice, I'd like to use this (eventually) on arm64. >=20 > * I'm aware of some arm64-specific groundwork we need to do before arm64 = can > use this. >=20 > So I think we're agreed. :) I'd love to have at least one more architecture come along for the ride as I do the next step. After this series, the largest chunk of time seems to be spent waiting for each AP as they transition to CPUHP_AP_ONLINE_IDLE and then all the way to CPUHP_ONLINE. So I'm going to look at making bringup_nonboot_cpus() prod *all* the APs to move to CPUHP_AP_ONLINE_IDLE without waiting for them to get there. Then do another pass waiting for that and prodding them to move to CPUHP_ONLINE. And then do a final pass of waiting for them to have got *there*. > > + int n =3D setup_max_cpus - num_online_cpus(); > > + > > + /* =E2=88=80 parallel pre-bringup state, bring N CPUs to it */ >=20 > I see you have a fancy maths keyboard. ;) Nah, standard UK layout keyboard. I just happen to remember U+2200 as it's *right* at the beginning of the mathematical symbols block and is fairly easy to type ;) > It might be worth using a few more words here for clarity, e.g. >=20 > /* > * Bring all nonboot CPUs through each pre-bringup state in turn > */ But it isn't *all* nonboot CPUs; it really is only up to N of them. --=-VjU8phqa4WulPKIa+BnH Content-Type: application/pkcs7-signature; name="smime.p7s" Content-Disposition: attachment; filename="smime.p7s" Content-Transfer-Encoding: base64 MIAGCSqGSIb3DQEHAqCAMIACAQExDzANBglghkgBZQMEAgEFADCABgkqhkiG9w0BBwEAAKCCECow ggUcMIIEBKADAgECAhEA4rtJSHkq7AnpxKUY8ZlYZjANBgkqhkiG9w0BAQsFADCBlzELMAkGA1UE BhMCR0IxGzAZBgNVBAgTEkdyZWF0ZXIgTWFuY2hlc3RlcjEQMA4GA1UEBxMHU2FsZm9yZDEaMBgG A1UEChMRQ09NT0RPIENBIExpbWl0ZWQxPTA7BgNVBAMTNENPTU9ETyBSU0EgQ2xpZW50IEF1dGhl bnRpY2F0aW9uIGFuZCBTZWN1cmUgRW1haWwgQ0EwHhcNMTkwMTAyMDAwMDAwWhcNMjIwMTAxMjM1 OTU5WjAkMSIwIAYJKoZIhvcNAQkBFhNkd213MkBpbmZyYWRlYWQub3JnMIIBIjANBgkqhkiG9w0B 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