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Wed, 21 Oct 2026 02:03:45 -0700 (PDT) Received: from [10.217.223.82] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3674198f1d8sm7902967eec.24.2026.10.21.02.03.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Oct 2026 02:03:44 -0700 (PDT) Message-ID: Date: Wed, 21 Oct 2026 14:33:39 +0530 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 7/7] arm64: dts: qcom: lemans: Enable lemans-sa8255p-ride board support To: Konrad Dybcio , Shawn Guo , Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Deepti Jaggi , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Nikunj Kela , Bartosz Golaszewski References: <20261015023711.721837-1-shengchao.guo@oss.qualcomm.com> <20261015023711.721837-8-shengchao.guo@oss.qualcomm.com> <45b54ff8-a2a6-4eaf-9d5b-cfd9bb40c459@oss.qualcomm.com> Content-Language: en-US From: Shazad Hussain In-Reply-To: <45b54ff8-a2a6-4eaf-9d5b-cfd9bb40c459@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDAzNSBTYWx0ZWRfX3Ll9IHMiPOkj YgOfLvCXuIlmEeLzaQCRDg4Ma6sJRfyNTn1ZJItxgF/YAdb/4ZLppPdWV4q3ETQB54btg20YB1g cVMF0mnHWWdNT7bOyVj4KJJT7b6lTC4= X-Proofpoint-ORIG-GUID: xaSJAFyqjPjRi5FVuHWpWYyfwJwPBRYK X-Proofpoint-GUID: xaSJAFyqjPjRi5FVuHWpWYyfwJwPBRYK X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDAzNSBTYWx0ZWRfX9u5T38uPetfD IM1WelADbn8XjRwRlv955K1LN+8QrjoTDTr2mBabmuVrU4ASPz8or2FA7Wi2z+EVz4v8gTygUa6 ryj6zsfMx12VyeUUrh7Z1b/k94Qx2gNDeYCHF5Th94dpc0NugbkLz+hdX8XaVrh5Iv/ztiJa0sM yz4qm9rIJs/aDtlFboDQPh148bziMwoENgqpPcrauU8k3jOQscc1uXWZjoOnkXNCuKinbJ1H42j XZV60BdpTjxBbpoE25cwfWfBsjP/1nus1BxKU0YROMwhmD7TKKPxr5Oo5r9zf/6jlGCicVkKmlA RdNVIUvE+5uO0F/ZHqd4GjcPaksC2voyRBARMwWDkEujKg4eOh6/yF7uKhHnYtV3arVcIvtvtB4 bq8k+xO+oflGCT0tkN4ZHy8/zZerEerzwvd2gTiMNsvASoCTWos6TvchWtXCXsu+mVhPFJHWiey Iayyxubzbg9O2bJIKSA== X-Authority-Analysis: v=2.4 cv=NLpAaE6g c=1 sm=1 tr=0 ts=6ad87ff2 cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=iDK90Gyl-TMhxqDKVhgA:9 a=QEXdDO2ut3YA:10 a=PxkB5W3o20Ba91AHUih5:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-21_02,2026-10-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 impostorscore=0 phishscore=0 spamscore=0 adultscore=0 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210035 On 10/20/2026 5:46 PM, Konrad Dybcio wrote: > On 10/15/26 4:37 AM, Shawn Guo wrote: >> From: Nikunj Kela >> >> Add initial device tree support for the Lemans SA8255P Ride board. Enable >> UFS storage, UART10 as the serial console, PCIe EP interfaces, thermal >> zones for PMM8654AU sensors, and SCMI protocol nodes. >> >> Co-developed-by: Shazad Hussain >> Signed-off-by: Shazad Hussain >> Signed-off-by: Nikunj Kela >> Co-developed-by: Deepti Jaggi >> Signed-off-by: Deepti Jaggi >> Reviewed-by: Bartosz Golaszewski >> Signed-off-by: Shawn Guo >> --- > > [...] > >> + thermal-zones { >> + pmm8654au_0_thermal: pm8255-0-thermal { >> + polling-delay-passive = <100>; > > Do we need the polling, is there no interrupt? > > [...] > > >> +&pcie0_ep { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pcie0_ep_clkreq_default &pcie0_ep_perst_default >> + &pcie0_ep_wake_default>; >> + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; >> + wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; > > This GPIO reference feels like a layering violation - the previous > commit promised TLMM is abstracted away Hi Konard, For PCIe EP, the TLMM gpio's are controlled via kernel and are not abstracted. Possibly we need to reserve them for kernel only. -Shazad > > Konrad