Re: [PATCH RFC 0/2] PCI: rockchip-host: Retry training and hot-reset a JMB585 on RK3399

[Shawn Lin <shawn.lin@rock-chips.com>]

在 2026/10/27 星期二 2:28, Igor Velkov 写道:
> Hi Shawn,
> 
> On 2026/10/26, Shawn Lin wrote:
>> The host cannot distinguish this case.
> 
> The controller seems to tell before the config read. On 26 Oct the
> link came back 2.9-4.5 ms after a hot reset in ~50 cases, all fine,
> and 10.9-35.4 ms in 8, each followed by an abort on the next config
> read. PCIE_CLIENT_BASIC_STATUS0 read 0x240 after each of 4 slow links
> and 0x1240 after each of 16 fast ones. What does bit 12 mean, and can
> the driver rely on it after link training?
> 

I have no idea about it. The PCIE_CLIENT_BASIC_STATUS0 says:

14:12  	RO  max_payload_size

So you are saying different MPS in different cases, not linking status.


>> You've tried PERST# with the patch 1 applied. So perhaps it's doesn't
>> help.
> 
> Patch 1 pulses PERST# only after a training timeout. With PERST# in
> the DT a slow link still occurred (25 ms, then an abort).
> Re-initializing the port, without PERST# or a power cycle, brought
> each of 4 slow links back in 2.9 ms with the endpoint answering.
> 
>> I've attached a vendor's debug patch, perhaps you could try it without
>> your patch.
> 
> It hooks do_serror() only and registers after pci_host_probe(). Here
> both SErrors and synchronous external aborts occur, at probe and on
> resume (the cover had that wrong), so we will move the hook before
> pci_host_probe() when we try it.

Yep.

> 
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