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Miller" , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Michal Simek , Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , Eric Dumazet , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rt-devel@lists.linux.dev, git@amd.com, neelisrinivas18@gmail.com Subject: Re: [PATCH net-next v4 1/8] dt-bindings: net: add Xilinx TSN Endpoint Ethernet MAC Message-ID: References: <20261113-patches_v2_external-v4-0-56bb26f042a4@amd.com> <20261113-patches_v2_external-v4-1-56bb26f042a4@amd.com> <13864fbe-6cd1-4d70-afee-bd3d3be163f3@lunn.ch> <4254be1a-f80e-4389-b04d-9fd10c1b77b7@amd.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <4254be1a-f80e-4389-b04d-9fd10c1b77b7@amd.com> > > Is this a synthesis parameter? No other switch that i know of has it > > in DT. The driver hard codes the value based on the compatible. Why > > does that not work for you? >   Yes, MAX_LEARNING_ENTRIES is a Vivado synthesis parameter of the IP >   (256 to 1920), and no register reports it I assume that will be fixed in the next version of the IP? Are there many other synthesis parameter which are not exported in registers? I just want to get an idea if this is a one off, or you are going to add lots of DT parameters in the next set of patches. >   The number of ports is fixed by the IP. The switch always has two >   external MAC ports and one internal endpoint port, and no configuration >   has more external MACs, so the binding never needs to grow another port. And that is signed off by top management? The next switch you design will be a fresh design, no reuse of the existing IP and will require a whole new DSA driver? >   The switch node follows the IP's register map. The switch fabric and the >   two MAC blocks are separate register windows of the switch IP, and each >   MAC window also holds that MAC's MDIO controller and PTP block. The PTP >   timer interrupt is shared by the whole switch, not owned by one port. > >   For these reasons I would prefer to keep the per-MAC resources on the >   switch node > > > > > > + switch@38000 { > > > + compatible = "xlnx,tsn-switch"; > > > + reg = <0x38000 0x8000>, > > > + <0x00000 0x14000>, > > > + <0x20000 0x14000>; > > > + reg-names = "switch", "mac1", "mac2"; I ask, because it would not be too hard to swap this address map around, put the switch registers first, and then the port registers, and you could have as many ports as you want. Back to what you just said: > each > MAC window also holds that MAC's MDIO controller and PTP block. So the MDIO controller and the PTP block are MAC properties, so should be inside the MAC node. > The PTP > timer interrupt is shared by the whole switch So that should be at the switch level. Andrew