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Thu, 01 Sep 2022 03:46:38 -0700 (PDT) Received: from [192.168.1.211] ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id h3-20020a056512220300b00492f45cbbfcsm2286586lfu.302.2022.09.01.03.46.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 01 Sep 2022 03:46:37 -0700 (PDT) Message-ID: Date: Thu, 1 Sep 2022 13:46:36 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.1.2 Subject: Re: [PATCH v6 4/6] clk: qcom: gpucc-sc7280: Add cx collapse reset support Content-Language: en-GB To: Philipp Zabel , Akhil P Oommen Cc: freedreno , dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Rob Clark , Bjorn Andersson , Stephen Boyd , Douglas Anderson , krzysztof.kozlowski@linaro.org, Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org References: <1661923108-789-1-git-send-email-quic_akhilpo@quicinc.com> <20220831104741.v6.4.I5e64ff4b77bb9079eb2edeea8a02585c9e76778f@changeid> <20220901103449.GC32271@pengutronix.de> From: Dmitry Baryshkov In-Reply-To: <20220901103449.GC32271@pengutronix.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 01/09/2022 13:34, Philipp Zabel wrote: > On Wed, Aug 31, 2022 at 10:48:25AM +0530, Akhil P Oommen wrote: >> Allow a consumer driver to poll for cx gdsc collapse through Reset >> framework. >> >> Signed-off-by: Akhil P Oommen >> Reviewed-by: Dmitry Baryshkov >> --- >> >> (no changes since v3) >> >> Changes in v3: >> - Convert 'struct qcom_reset_ops cx_gdsc_reset' to 'static const' (Krzysztof) >> >> Changes in v2: >> - Minor update to use the updated custom reset ops implementation >> >> drivers/clk/qcom/gpucc-sc7280.c | 10 ++++++++++ >> 1 file changed, 10 insertions(+) >> >> diff --git a/drivers/clk/qcom/gpucc-sc7280.c b/drivers/clk/qcom/gpucc-sc7280.c >> index 9a832f2..fece3f4 100644 >> --- a/drivers/clk/qcom/gpucc-sc7280.c >> +++ b/drivers/clk/qcom/gpucc-sc7280.c >> @@ -433,12 +433,22 @@ static const struct regmap_config gpu_cc_sc7280_regmap_config = { >> .fast_io = true, >> }; >> >> +static const struct qcom_reset_ops cx_gdsc_reset = { >> + .reset = gdsc_wait_for_collapse, > > This should be accompanied by a comment explaining the not-quite-reset > nature of this workaround, i.e. what is the prerequisite for this to > actually work as expected? > >> +}; >> + >> +static const struct qcom_reset_map gpucc_sc7280_resets[] = { >> + [GPU_CX_COLLAPSE] = { .ops = &cx_gdsc_reset, .priv = &cx_gdsc }, >> +}; >> + >> static const struct qcom_cc_desc gpu_cc_sc7280_desc = { >> .config = &gpu_cc_sc7280_regmap_config, >> .clks = gpu_cc_sc7280_clocks, >> .num_clks = ARRAY_SIZE(gpu_cc_sc7280_clocks), >> .gdscs = gpu_cc_sc7180_gdscs, >> .num_gdscs = ARRAY_SIZE(gpu_cc_sc7180_gdscs), >> + .resets = gpucc_sc7280_resets, >> + .num_resets = ARRAY_SIZE(gpucc_sc7280_resets), > > See my comment on patch 2. I think instead of adding a const struct > qcom_reset_ops * to gpucc_sc7280_resets, this should just add a const > struct reset_control * to gpu_cc_sc7280_desc. While this will work for the sc7280, the platform that Akhil was developing, this will not work for other platforms (like sm8250), where the dispcc also provides traditional BCR resets. -- With best wishes Dmitry