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Fri, 08 Aug 2025 13:27:02 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 578DR1eI022341 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 8 Aug 2025 13:27:01 GMT Received: from [10.216.4.18] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 8 Aug 2025 06:26:58 -0700 Message-ID: Date: Fri, 8 Aug 2025 18:56:55 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v4 2/3] virtio-spi: Add virtio-spi.h To: Haixu Cui , , , , , , , , CC: References: <20250401033621.1614194-1-quic_haixcui@quicinc.com> <20250401033621.1614194-3-quic_haixcui@quicinc.com> Content-Language: en-US From: Jyothi Kumar Seerapu In-Reply-To: <20250401033621.1614194-3-quic_haixcui@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA2MDAwOSBTYWx0ZWRfX/JCZxe7g0nnL t+n/LQOv4gtpWWQPy41YNb0rmLIGRy/j2WAzTDir/SCiGFeW10N4BjxGPS4NxikUNE7RYsiLqCy TIbvn2VxwVJkxUD6zRTdRZJthRW/nnnqBcS4cctg7jOfQsHxxJtWPD/uV1c397mqg1S2fGB2xRB 35J8Oy4wSGLPV1oT2mKO116ZGwdGtLyyrEAAaWJjSyipfAbuJzD9IlN1rEZiT8szVl2pmdW4NCL UtA5OITOP478YT10XOhPfG7yUAaUFnYGBgn/5nCkbnps4GD6ZOOI57D/5M2+QeyQj/Wb4kfc/Be 8HIyY9d68oe/rlkiXGA/bFMZ2F2+3apKBk7Fg8BttkwR6JNP8YyfZPgb6TZTHKiVkVEGIjewV0h VhKUBLdr X-Authority-Analysis: v=2.4 cv=Ha4UTjE8 c=1 sm=1 tr=0 ts=6895fb26 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=COk6AnOGAAAA:8 a=H0x4yso8YIw0H6KSdXIA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: NOzltO_rZ0l2WfN2p6APArjKFMZl-zjW X-Proofpoint-GUID: NOzltO_rZ0l2WfN2p6APArjKFMZl-zjW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-08_04,2025-08-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 malwarescore=0 clxscore=1011 phishscore=0 bulkscore=0 adultscore=0 suspectscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508060009 On 4/1/2025 9:06 AM, Haixu Cui wrote: > Add virtio-spi.h header for virtio SPI. > > Signed-off-by: Haixu Cui > --- > include/uapi/linux/virtio_spi.h | 185 ++++++++++++++++++++++++++++++++ > 1 file changed, 185 insertions(+) > create mode 100644 include/uapi/linux/virtio_spi.h > > diff --git a/include/uapi/linux/virtio_spi.h b/include/uapi/linux/virtio_spi.h > new file mode 100644 > index 000000000000..1cb6da912345 > --- /dev/null > +++ b/include/uapi/linux/virtio_spi.h > @@ -0,0 +1,185 @@ > +/* SPDX-License-Identifier: BSD-3-Clause */ > +/* > + * Copyright (C) 2025 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > +#ifndef _LINUX_VIRTIO_VIRTIO_SPI_H > +#define _LINUX_VIRTIO_VIRTIO_SPI_H > + > +#include > +#include > +#include > +#include > + > +/* Sample data on trailing clock edge */ > +#define VIRTIO_SPI_CPHA (1 << 0) > +/* Clock is high when IDLE */ > +#define VIRTIO_SPI_CPOL (1 << 1) > +/* Chip Select is active high */ > +#define VIRTIO_SPI_CS_HIGH (1 << 2) > +/* Transmit LSB first */ > +#define VIRTIO_SPI_MODE_LSB_FIRST (1 << 3) > +/* Loopback mode */ > +#define VIRTIO_SPI_MODE_LOOP (1 << 4) > + > +/* > + * All config fields are read-only for the Virtio SPI driver > + * > + * @cs_max_number: maximum number of chipselect the host SPI controller > + * supports. > + * @cs_change_supported: indicates if the host SPI controller supports to toggle > + * chipselect after each transfer in one message: > + * 0: unsupported, chipselect will be kept in active state throughout the > + * message transaction; > + * 1: supported. > + * Note: Message here contains a sequence of SPI transfers. > + * @tx_nbits_supported: indicates the supported number of bit for writing: > + * bit 0: DUAL (2-bit transfer), 1 for supported > + * bit 1: QUAD (4-bit transfer), 1 for supported > + * bit 2: OCTAL (8-bit transfer), 1 for supported > + * other bits are reserved as 0, 1-bit transfer is always supported. > + * @rx_nbits_supported: indicates the supported number of bit for reading: > + * bit 0: DUAL (2-bit transfer), 1 for supported > + * bit 1: QUAD (4-bit transfer), 1 for supported > + * bit 2: OCTAL (8-bit transfer), 1 for supported > + * other bits are reserved as 0, 1-bit transfer is always supported. > + * @bits_per_word_mask: mask indicating which values of bits_per_word are > + * supported. If not set, no limitation for bits_per_word. > + * @mode_func_supported: indicates the following features are supported or not: > + * bit 0-1: CPHA feature > + * 0b00: invalid, should support as least one CPHA setting > + * 0b01: supports CPHA=0 only > + * 0b10: supports CPHA=1 only > + * 0b11: supports CPHA=0 and CPHA=1. > + * bit 2-3: CPOL feature > + * 0b00: invalid, should support as least one CPOL setting > + * 0b01: supports CPOL=0 only > + * 0b10: supports CPOL=1 only > + * 0b11: supports CPOL=0 and CPOL=1. > + * bit 4: chipselect active high feature, 0 for unsupported and 1 for > + * supported, chipselect active low should always be supported. > + * bit 5: LSB first feature, 0 for unsupported and 1 for supported, > + * MSB first should always be supported. > + * bit 6: loopback mode feature, 0 for unsupported and 1 for supported, > + * normal mode should always be supported. > + * @max_freq_hz: the maximum clock rate supported in Hz unit, 0 means no > + * limitation for transfer speed. > + * @max_word_delay_ns: the maximum word delay supported in ns unit, > + * 0 means word delay feature is unsupported. > + * Note: Just as one message contains a sequence of transfers, > + * one transfer may contain a sequence of words. Instead of adding "Note:", can we update it like this? @max_word_delay_ns: Maximum word delay supported, in nanoseconds. A value of 0 indicates that word delay is unsupported. Each transfer may consist of a sequence of words. > + * @max_cs_setup_ns: the maximum delay supported after chipselect is asserted, > + * in ns unit, 0 means delay is not supported to introduce after chipselect is > + * asserted. > + * @max_cs_hold_ns: the maximum delay supported before chipselect is deasserted, > + * in ns unit, 0 means delay is not supported to introduce before chipselect > + * is deasserted. > + * @max_cs_incative_ns: maximum delay supported after chipselect is deasserted, > + * in ns unit, 0 means delay is not supported to introduce after chipselect is > + * deasserted. > + */ > +struct virtio_spi_config { > + /* # of /dev/spidev.CS with CS=0..chip_select_max_number -1 */ > + __u8 cs_max_number; > + __u8 cs_change_supported; > +#define VIRTIO_SPI_RX_TX_SUPPORT_DUAL (1 << 0) > +#define VIRTIO_SPI_RX_TX_SUPPORT_QUAD (1 << 1) > +#define VIRTIO_SPI_RX_TX_SUPPORT_OCTAL (1 << 2) > + __u8 tx_nbits_supported; > + __u8 rx_nbits_supported; > + __le32 bits_per_word_mask; > +#define VIRTIO_SPI_MF_SUPPORT_CPHA_0 (1 << 0) > +#define VIRTIO_SPI_MF_SUPPORT_CPHA_1 (1 << 1) > +#define VIRTIO_SPI_MF_SUPPORT_CPOL_0 (1 << 2) > +#define VIRTIO_SPI_MF_SUPPORT_CPOL_1 (1 << 3) > +#define VIRTIO_SPI_MF_SUPPORT_CS_HIGH (1 << 4) > +#define VIRTIO_SPI_MF_SUPPORT_LSB_FIRST (1 << 5) > +#define VIRTIO_SPI_MF_SUPPORT_LOOPBACK (1 << 6) > + __le32 mode_func_supported; > + __le32 max_freq_hz; > + __le32 max_word_delay_ns; > + __le32 max_cs_setup_ns; > + __le32 max_cs_hold_ns; > + __le32 max_cs_inactive_ns; > +}; > + > +/* > + * @chip_select_id: chipselect index the SPI transfer used. > + * > + * @bits_per_word: the number of bits in each SPI transfer word. > + * > + * @cs_change: whether to deselect device after finishing this transfer > + * before starting the next transfer, 0 means cs keep asserted and > + * 1 means cs deasserted then asserted again. > + * > + * @tx_nbits: bus width for write transfer. > + * 0,1: bus width is 1, also known as SINGLE Do you mean to say that a value of 0 defaults to SINGLE?> + * 2 : bus width is 2, also known as DUAL > + * 4 : bus width is 4, also known as QUAD > + * 8 : bus width is 8, also known as OCTAL > + * other values are invalid. > + * > + * @rx_nbits: bus width for read transfer. > + * 0,1: bus width is 1, also known as SINGLE > + * 2 : bus width is 2, also known as DUAL > + * 4 : bus width is 4, also known as QUAD > + * 8 : bus width is 8, also known as OCTAL > + * other values are invalid. > + * > + * @reserved: for future use. > + * > + * @mode: SPI transfer mode. > + * bit 0: CPHA, determines the timing (i.e. phase) of the data > + * bits relative to the clock pulses.For CPHA=0, the > + * "out" side changes the data on the trailing edge of the > + * preceding clock cycle, while the "in" side captures the data > + * on (or shortly after) the leading edge of the clock cycle. > + * For CPHA=1, the "out" side changes the data on the leading > + * edge of the current clock cycle, while the "in" side > + * captures the data on (or shortly after) the trailing edge of > + * the clock cycle. > + * bit 1: CPOL, determines the polarity of the clock. CPOL=0 is a > + * clock which idles at 0, and each cycle consists of a pulse > + * of 1. CPOL=1 is a clock which idles at 1, and each cycle > + * consists of a pulse of 0. > + * bit 2: CS_HIGH, if 1, chip select active high, else active low. > + * bit 3: LSB_FIRST, determines per-word bits-on-wire, if 0, MSB > + * first, else LSB first. > + * bit 4: LOOP, loopback mode. > + * > + * @freq: the transfer speed in Hz. > + * > + * @word_delay_ns: delay to be inserted between consecutive words of a > + * transfer, in ns unit. > + * > + * @cs_setup_ns: delay to be introduced after CS is asserted, in ns > + * unit. > + * > + * @cs_delay_hold_ns: delay to be introduced before CS is deasserted > + * for each transfer, in ns unit. > + * > + * @cs_change_delay_inactive_ns: delay to be introduced after CS is > + * deasserted and before next asserted, in ns unit. > + */ > +struct spi_transfer_head { > + __u8 chip_select_id; > + __u8 bits_per_word; > + __u8 cs_change; > + __u8 tx_nbits; > + __u8 rx_nbits; > + __u8 reserved[3]; > + __le32 mode; > + __le32 freq; > + __le32 word_delay_ns; > + __le32 cs_setup_ns; > + __le32 cs_delay_hold_ns; > + __le32 cs_change_delay_inactive_ns; > +}; > + > +struct spi_transfer_result { > +#define VIRTIO_SPI_TRANS_OK 0 > +#define VIRTIO_SPI_PARAM_ERR 1 > +#define VIRTIO_SPI_TRANS_ERR 2 > + u8 result; > +}; > + > +#endif /* #ifndef _LINUX_VIRTIO_VIRTIO_SPI_H */