Re: [PATCH v3 8/8] mmc: sdhci-cadence: add Altera Agilex5 SD6HC support

[Philipp Zabel <p.zabel@pengutronix.de>]

On Fr, 2026-07-24 at 07:50 -0700, Tanmay Kathpalia wrote:
> The Altera Agilex5 SoC integrates a Cadence SD6HC controller that needs
> platform-specific configuration to operate correctly.
> 
> The SoC requires three named resets: "sdhc-reset", "combophy", and
> "sdmmc-ocp". All three are exclusive and must be asserted together before
> being released, so the SDHCI, SoftPHY, and OCP/AXI clock domains cross the
> reset boundary simultaneously. SoftPHY is shared with NAND at the SoC
> level, but only one of SDMMC or NAND is enabled on a given board.
> 
> The IOMMU maps DMA addresses within a 40-bit physical address space, so
> the DMA mask is capped at 40 bits to prevent allocation beyond the
> controller's reach.
> 
> The silicon requires the MULTIBLOCK_READ_ACMD12, CAP_CLOCK_BASE_BROKEN,
> PRESET_VALUE_BROKEN, and ACMD23_BROKEN quirks. Since
> CAP_CLOCK_BASE_BROKEN prevents reading the base clock from the
> capabilities register, the maximum clock is supplied from the platform
> clock instead.
> 
> Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
> ---
>  drivers/mmc/host/sdhci-cadence-core.c | 113 ++++++++++++++++++++++++++
>  1 file changed, 113 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-cadence-core.c b/drivers/mmc/host/sdhci-cadence-core.c
> index 18846acc0b11..24130655a385 100644
> --- a/drivers/mmc/host/sdhci-cadence-core.c
> +++ b/drivers/mmc/host/sdhci-cadence-core.c
[...]
> @@ -462,6 +481,72 @@ static int elba_drv_init(struct platform_device *pdev)
>  	return 0;
>  }
>  
> +static int sdhci_cdns6_agilex5_init(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct reset_control *rst_sdhc;
> +	struct reset_control *rst_combophy;
> +	struct reset_control *rst_ocp;
> +	int ret;
> +
> +	/*
> +	 * Assert SDHCI, SoftPHY (combophy), and SDMMC OCP/AXI resets together
> +	 * so their active periods overlap before all domains are released.
> +	 * SoftPHY is shared with NAND, but only one of SDMMC
> +	 * or NAND is enabled on a given board.
> +	 */
> +	rst_sdhc = devm_reset_control_get_exclusive(dev, "sdhc-reset");
> +	if (IS_ERR(rst_sdhc))
> +		return dev_err_probe(dev, PTR_ERR(rst_sdhc), "failed to get sdhc-reset\n");
> +
> +	rst_combophy = devm_reset_control_get_exclusive(dev, "combophy");
> +	if (IS_ERR(rst_combophy))
> +		return dev_err_probe(dev, PTR_ERR(rst_combophy), "failed to get combophy reset\n");
> +
> +	rst_ocp = devm_reset_control_get_exclusive(dev, "sdmmc-ocp");
> +	if (IS_ERR(rst_ocp))
> +		return dev_err_probe(dev, PTR_ERR(rst_ocp), "failed to get sdmmc-ocp reset\n");

This looks like it could be simplified with
devm_reset_control_bulk_get_exclusive().

regards
Philipp