From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.4 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74290C433DB for ; Mon, 18 Jan 2021 15:42:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 38888206DC for ; Mon, 18 Jan 2021 15:42:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2393488AbhARPkr (ORCPT ); Mon, 18 Jan 2021 10:40:47 -0500 Received: from foss.arm.com ([217.140.110.172]:38070 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388441AbhARPgp (ORCPT ); Mon, 18 Jan 2021 10:36:45 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1ACD21FB; Mon, 18 Jan 2021 07:35:58 -0800 (PST) Received: from [10.37.8.29] (unknown [10.37.8.29]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 66E603F68F; Mon, 18 Jan 2021 07:35:55 -0800 (PST) Subject: Re: [PATCH v3 3/4] arm64: mte: Enable async tag check fault From: Vincenzo Frascino To: Mark Rutland Cc: Catalin Marinas , Branislav Rankov , Marco Elver , Andrey Konovalov , Evgenii Stepanov , linux-kernel@vger.kernel.org, kasan-dev@googlegroups.com, Alexander Potapenko , linux-arm-kernel@lists.infradead.org, Andrey Ryabinin , Will Deacon , Dmitry Vyukov References: <20210115120043.50023-1-vincenzo.frascino@arm.com> <20210115120043.50023-4-vincenzo.frascino@arm.com> <20210118125715.GA4483@gaia> <20210118141429.GC31263@C02TD0UTHF1T.local> <1c0577c1-bf73-2c00-b137-9f7251afd20e@arm.com> Message-ID: Date: Mon, 18 Jan 2021 15:39:43 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <1c0577c1-bf73-2c00-b137-9f7251afd20e@arm.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 1/18/21 2:48 PM, Vincenzo Frascino wrote: >> Are you aware of cases where the TFSR_EL1 value is read other than by an >> MRS? e.g. are there any cases where checks are elided if TF1 is set? If >> so, we may need the ISB to order the direct write against subsequent >> indirect reads. >> > Thank you for the explanation. I am not aware of any case in which TFSR_EL1 is > read other then by an MRS. Based on the ARM DDI 0487F.c (J1-7626) TF0/TF1 are > always set to '1' without being accessed before. I will check with the > architects for further clarification and if this is correct I will remove the > isb() in the next version. > I spoke to the architects and I confirm that the isb() can be removed. -- Regards, Vincenzo