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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af91a1e82bbsm1310874666b.81.2025.08.07.06.07.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 07 Aug 2025 06:07:50 -0700 (PDT) Message-ID: Date: Thu, 7 Aug 2025 15:07:47 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/7] clk: qcom: Add TCSR clock driver for Glymur To: Taniya Das , Abel Vesa Cc: kernel@oss.qualcomm.com, Pankaj Patil , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250729-glymur-gcc-tcsrcc-rpmhcc-v3-0-227cfe5c8ef4@oss.qualcomm.com> <20250729-glymur-gcc-tcsrcc-rpmhcc-v3-3-227cfe5c8ef4@oss.qualcomm.com> <784545d0-2173-4a8b-9d5d-bee11226351e@oss.qualcomm.com> <3fc425fd-39fa-4efc-bc98-da86a88bfb1a@oss.qualcomm.com> <9e3b4706-c61a-4d69-be84-a5b6fc90eb35@oss.qualcomm.com> <462b4010-fd79-4682-b9d2-31ffdd53b75a@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <462b4010-fd79-4682-b9d2-31ffdd53b75a@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA2MDAwOSBTYWx0ZWRfX8CbhykK5nZBY OLoYmv3T8TLiwP/HJyMwVt6j7LRz7qMNHyfaeIIGYLJ6qafg6pwdQRROndIXA9Pb1DSjCbeuA+8 wqBhsrw27dLwj9P7l+B7GBzTyimhytRwDSoVpDy6E5aMZyCjPNI+hChvrYN0DXtF8hjjtk3RY/W Tp18vGeYxn2c8BTP32gL10TBB/uCRAY0+40EugOPicibgkGoEOsha6JJEQosdfBAqPq19zrDewg UGROybY3S8F/jGUbd/zAcJNpY6U+o8/irPmSi/u+I3B8N1AVm08NIexLtfDkI0r4Lqbtq462fIm mgP6zXHm/AmyWLAHL3GlgA/LMPO9wkfxUolEV4ZS4hTCTIu2VWQTZELj0Gw5Co5mD9QVrYHlRYR FmsyVfPs X-Authority-Analysis: v=2.4 cv=Ha4UTjE8 c=1 sm=1 tr=0 ts=6894a528 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=PLusG5baLZIICTn4gS8A:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-ORIG-GUID: T1wpG78NI8pk8tQiATX-SG_b2Wug7cJv X-Proofpoint-GUID: T1wpG78NI8pk8tQiATX-SG_b2Wug7cJv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-07_02,2025-08-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 phishscore=0 bulkscore=0 adultscore=0 suspectscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508060009 On 8/6/25 12:21 PM, Taniya Das wrote: > > > On 8/6/2025 3:34 PM, Konrad Dybcio wrote: >> On 8/4/25 4:21 PM, Taniya Das wrote: >>> >>> >>> On 8/4/2025 6:40 PM, Konrad Dybcio wrote: >>>> On 8/4/25 11:00 AM, Taniya Das wrote: >>>>> >>>>> >>>>> On 8/1/2025 5:24 PM, Konrad Dybcio wrote: >>>>>> On 8/1/25 7:31 AM, Abel Vesa wrote: >>>>>>> On 25-08-01 10:02:15, Taniya Das wrote: >>>>>>>> >>>>>>>> >>>>>>>> On 7/30/2025 4:55 PM, Abel Vesa wrote: >>>>>>>>> On 25-07-29 11:12:37, Taniya Das wrote: >>>>>>>>>> Add a clock driver for the TCSR clock controller found on Glymur, which >>>>>>>>>> provides refclks for PCIE, USB, and UFS. >>>>>>>>>> >>>>>>>>>> Signed-off-by: Taniya Das >>>>>>>>>> --- >>>>>>>>>> drivers/clk/qcom/Kconfig | 8 ++ >>>>>>>>>> drivers/clk/qcom/Makefile | 1 + >>>>>>>>>> drivers/clk/qcom/tcsrcc-glymur.c | 257 +++++++++++++++++++++++++++++++++++++++ >>>>>>>>>> 3 files changed, 266 insertions(+) >>>>>>>>>> >>>>>>>>> >>>>>>>>> [...] >>>>>>>>> >>>>>>>>>> + >>>>>>>>>> +static struct clk_branch tcsr_edp_clkref_en = { >>>>>>>>>> + .halt_reg = 0x1c, >>>>>>>>>> + .halt_check = BRANCH_HALT_DELAY, >>>>>>>>>> + .clkr = { >>>>>>>>>> + .enable_reg = 0x1c, >>>>>>>>>> + .enable_mask = BIT(0), >>>>>>>>>> + .hw.init = &(const struct clk_init_data) { >>>>>>>>>> + .name = "tcsr_edp_clkref_en", >>>>>>>>>> + .ops = &clk_branch2_ops, >>>>>>>>> >>>>>>>>> As discussed off-list, these clocks need to have the bi_tcxo as parent. >>>>>>>>> >>>>>>>>> Otherwise, as far as the CCF is concerned these clocks will have rate 0, >>>>>>>>> which is obviously not the case. >>>>>>>>> >>>>>>>>> Bringing this here since there is a disconnect between X Elite and >>>>>>>>> Glymur w.r.t this now. >>>>>>>> >>>>>>>> >>>>>>>> The ref clocks are not required to be have a parent of bi_tcxo as these >>>>>>>> ideally can be left enabled(as a subsystem requirement) even if HLOS >>>>>>>> (APSS) goes to suspend. With the bi_tcxo parent the ARC vote from >>>>>>>> HLOS/APSS will not allow APSS to collapse. >>>>>>> >>>>>>> Is there a scenario where the APSS is collapsed and still the ref clock >>>>>>> needs to stay enabled ? Sorry, this doesn't make sense to me. >>>>>> >>>>>> MDSS is capable of displaying things from a buffer when the CPU is off, >>>>>> AFAICU >>>>>> >>>>>> We can do CXO_AO instead to have it auto-collapse if it's just Linux >>>>>> requesting it to stay on, I think. >>>>>> >>>>> >>>>> Thanks Konrad for adding the display use case. >>>>> Abel, we earlier also had some PCIe, USB use cases where we had to leave >>>>> the ref clocks ON and APSS could collapse. >>>> >>>> XO votes will prevent CX collapse, not APSS collapse. CX also powers >>>> USB and PCIe so that only makes sense. >>>> >>>> I think it's fair to just stick XO as the parent of every refclock >>>> today and think about the what-ifs (such as the mdss case I mentioned >>>> above) later - especially since we have no infra to take full advantage >>>> of it today (non-APSS RSCs etc.) >>>> >>> >>> When ref clock have been part of GCC, then also they didn't have any xo >>> as the parent, similar design we kept when it was moved to TCSR as well. >> >> Perhaps we've been running on luck (i.e. XO votes being cast through >> another device / clock as a second order effect) all this time.. I'd >> happily move towards formal correctness. >> > > I would like to stay with no XO linkage to TCSR. Any driver has specific > XO requirement should vote for the rpmhcc XO or XO_AO. Every driver has an XO requirement, as we happen not to have any other crystals onboard.. The clock plan says that these refclks are direct children of XO too Konrad