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AFNElJ/hff6FQZF5bLCGck7moK8zy9Q0t03Aae3BOXs8pA+WLeBGU2KmVrJoMaSB8RHEN8fKc2eB5gz3I//6RDU=@vger.kernel.org X-Gm-Message-State: AOJu0YyoNf26KjJzt9t7OJcNmvHwPgePPEDu93LbtHkGR/FbZJdBS9wx H8NBxlPQocEOLWF8M7zQg/zFB66RF/IfCPT1TxvpboXeGMsW2OJTl1Kbr/G3l1WUjayoxVdK18S QOSDKzFfyTwsY/F+n92RpooII4w== X-Received: from jabjq11.prod.google.com ([2002:a05:6638:8d8b:b0:5e2:40af:256a]) (user=coltonlewis job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6808:2444:b0:467:d71:7f1a with SMTP id 5614622812f47-4896c8a3f7cmr734469b6e.21.1781825411153; Thu, 18 Jun 2026 16:30:11 -0700 (PDT) Date: Thu, 18 Jun 2026 23:30:10 +0000 In-Reply-To: (message from wuyifan on Tue, 16 Jun 2026 17:07:48 +0800) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Message-ID: Subject: Re: [PATCH v7 11/20] KVM: arm64: Enforce PMU event filter at vcpu_load() From: Colton Lewis To: wuyifan Cc: kvm@vger.kernel.org, alexandru.elisei@arm.com, pbonzini@redhat.com, corbet@lwn.net, linux@armlinux.org.uk, catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, oliver.upton@linux.dev, mizhang@google.com, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, mark.rutland@arm.com, shuah@kernel.org, gankulkarni@os.amperecomputing.com, james.clark@linaro.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org, wangyushan12@huawei.com, fanghao11@huawei.com, wangzhou1@hisilicon.com, prime.zeng@hisilicon.com, xuwei5@huawei.com Content-Type: text/plain; charset="UTF-8"; format=flowed; delsp=yes Hi Yifan, thanks for the review. wuyifan writes: > Hi Colton, > On 5/5/2026 5:18 AM, Colton Lewis wrote: >> + for_each_set_bit(i, &guest_counters, ARMPMU_MAX_HWEVENTS) { >> + if (i == ARMV8_PMU_CYCLE_IDX) { >> + val = __vcpu_sys_reg(vcpu, PMCCFILTR_EL0); >> + evsel = ARMV8_PMUV3_PERFCTR_CPU_CYCLES; >> + } else { >> + val = __vcpu_sys_reg(vcpu, PMEVTYPER0_EL0 + i); >> + evsel = val & kvm_pmu_event_mask(vcpu->kvm); >> + } >> + >> + guest_include_el2 = (val & ARMV8_PMU_INCLUDE_EL2); >> + val &= ~evtyper_clr; >> + >> + if (unlikely(is_hyp_ctxt(vcpu)) && guest_include_el2) >> + val &= ~ARMV8_PMU_EXCLUDE_EL1; >> + >> + if (vcpu->kvm->arch.pmu_filter && >> + !test_bit(evsel, vcpu->kvm->arch.pmu_filter)) >> + val |= evtyper_set; >> + >> + if (i == ARMV8_PMU_CYCLE_IDX) { >> + write_sysreg(val, pmccntr_el0); > This should be pmccfiltr_el0. > Writing the filter bits to pmccntr_el0 would corrupt the cycle count > value. Yes it should. I found that and thought I corrected it before I sent out the series. Thanks for catching it. >> + } else { >> + write_sysreg(i, pmselr_el0); >> + write_sysreg(val, pmxevtyper_el0); >> + } >> + } >> +} > Thanks, > Yifan