From: Arne Georg Gleditsch <argggh@dolphinics.no>
To: "J.A. Magallón" <jamagallon@ono.com>
Cc: linux-kernel@vger.kernel.org
Subject: Re: Opteron box and 4Gb memory
Date: Fri, 26 Oct 2007 10:08:08 +0200 [thread overview]
Message-ID: <kjmsl3yuwlz.fsf@pelargir.dolphinics.no> (raw)
In-Reply-To: <20071026004434.50c73dd3@werewolf> ("J.A. =?iso-8859-1?Q?Maga?= =?iso-8859-1?Q?ll=F3n=22's?= message of "Fri\, 26 Oct 2007 00\:44\:34 +0200")
"J.A. Magallón" <jamagallon@ono.com> writes:
> Software Memory Hole
> When "Enabled", allows software memory remapping around the memory
> hole. Options are Enabled and Disabled.
>
> Hardware Memory Hole
> When "Enabled", allows software memory remapping around the memory
> hole. Options are Enabled and Disabled. Note: this is only supported by
> Rev E0 processors and above.
> ( I have two Opteron 275 processors, no idea about revision)
The configuration register used to to reclaim DRAM lost to an MMIO
hole was introduced with revision E of the gen1 Opterons. (This
feature is supposed to work both in interleaved and non-interleaved
mode.) What does /proc/cpuinfo say? (On both?)
(Still, even without this your BIOS should be able to map your memory
so that you are able to use all 4G. Provided you disable
interleaving, I can't see that there's anything stopping the BIOS from
mapping the memory from node 1 to 0-2G and the memory from node 2 to
4-6G, leaving a 2G hole for MMIO and other junk. Whether your BIOS
actually supports this is another matter.)
--
Arne.
next prev parent reply other threads:[~2007-10-26 8:39 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-10-25 21:09 J.A. Magallon
2007-10-25 21:58 ` H. Peter Anvin
2007-10-25 22:44 ` J.A. Magallón
2007-10-26 8:08 ` Arne Georg Gleditsch [this message]
2007-10-25 22:45 ` Rafael J. Wysocki
2007-11-04 23:18 ` J.A. Magallón
2007-11-05 18:10 ` Lennart Sorensen
2007-11-05 18:45 ` J.A. Magallón
2007-11-05 18:50 ` Lennart Sorensen
2007-11-05 23:03 ` J.A. Magallón
2007-11-08 18:08 ` Lennart Sorensen
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