From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758176AbcC2UQ5 (ORCPT ); Tue, 29 Mar 2016 16:16:57 -0400 Received: from shadbolt.e.decadent.org.uk ([88.96.1.126]:45154 "EHLO shadbolt.e.decadent.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758015AbcC2UE4 (ORCPT ); Tue, 29 Mar 2016 16:04:56 -0400 Content-Type: text/plain; charset="UTF-8" Content-Disposition: inline Content-Transfer-Encoding: 8bit MIME-Version: 1.0 From: Ben Hutchings To: linux-kernel@vger.kernel.org, stable@vger.kernel.org CC: akpm@linux-foundation.org, "Harvey Hunt" , "Tejun Heo" Date: Tue, 29 Mar 2016 20:18:22 +0100 Message-ID: X-Mailer: LinuxStableQueue (scripts by bwh) Subject: [PATCH 3.2 40/62] libata: Align ata_device's id on a cacheline In-Reply-To: X-SA-Exim-Connect-IP: 213.146.164.225 X-SA-Exim-Mail-From: ben@decadent.org.uk X-SA-Exim-Scanned: No (on shadbolt.decadent.org.uk); SAEximRunCond expanded to false Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 3.2.79-rc1 review patch. If anyone has any objections, please let me know. ------------------ From: Harvey Hunt commit 4ee34ea3a12396f35b26d90a094c75db95080baa upstream. The id buffer in ata_device is a DMA target, but it isn't explicitly cacheline aligned. Due to this, adjacent fields can be overwritten with stale data from memory on non coherent architectures. As a result, the kernel is sometimes unable to communicate with an ATA device. Fix this by ensuring that the id buffer is cacheline aligned. This issue is similar to that fixed by Commit 84bda12af31f ("libata: align ap->sector_buf"). Signed-off-by: Harvey Hunt Cc: linux-kernel@vger.kernel.org Signed-off-by: Tejun Heo Signed-off-by: Ben Hutchings --- include/linux/libata.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/include/linux/libata.h +++ b/include/linux/libata.h @@ -662,7 +662,7 @@ struct ata_device { union { u16 id[ATA_ID_WORDS]; /* IDENTIFY xxx DEVICE data */ u32 gscr[SATA_PMP_GSCR_DWORDS]; /* PMP GSCR block */ - }; + } ____cacheline_aligned; /* error history */ int spdn_cnt;