From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752576AbdKVCkx (ORCPT ); Tue, 21 Nov 2017 21:40:53 -0500 Received: from shadbolt.e.decadent.org.uk ([88.96.1.126]:57458 "EHLO shadbolt.e.decadent.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752429AbdKVCkn (ORCPT ); Tue, 21 Nov 2017 21:40:43 -0500 Content-Type: text/plain; charset="UTF-8" Content-Disposition: inline Content-Transfer-Encoding: 8bit MIME-Version: 1.0 From: Ben Hutchings To: linux-kernel@vger.kernel.org, stable@vger.kernel.org CC: akpm@linux-foundation.org, "Jonathan Cameron" , "Lorenzo Bianconi" , "Lorenzo Bianconi" Date: Wed, 22 Nov 2017 01:58:12 +0000 Message-ID: X-Mailer: LinuxStableQueue (scripts by bwh) Subject: [PATCH 3.16 033/133] iio: accel: st_accel: fix data-ready line configuration In-Reply-To: X-SA-Exim-Connect-IP: 2a02:8011:400e:2:6f00:88c8:c921:d332 X-SA-Exim-Mail-From: ben@decadent.org.uk X-SA-Exim-Scanned: No (on shadbolt.decadent.org.uk); SAEximRunCond expanded to false Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 3.16.51-rc1 review patch. If anyone has any objections, please let me know. ------------------ From: Lorenzo Bianconi commit 4303741f99d617c1fc3c9069195d3d620c2f88c4 upstream. Remove int2 configuration parameter for LIS3DH, LSM303DLHC, LSM330D, LSM330DL, LSM330DLC, LSM303AGR, LIS2DH12 and LNG2DM since these devices export just int1 as data-ready line Fixes: 23cde4d65cc7 (iio: Added platform data to select the DRDY pin) Fixes: dcdb0a78cab3 (iio: accel: st_accel: add support to lng2dm) Signed-off-by: Lorenzo Bianconi Signed-off-by: Jonathan Cameron [bwh: Backported to 3.16: - Update the macro used to fill in this field - Drop change for LNG2DM] Signed-off-by: Ben Hutchings --- drivers/iio/accel/st_accel_core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) --- a/drivers/iio/accel/st_accel_core.c +++ b/drivers/iio/accel/st_accel_core.c @@ -66,7 +66,7 @@ #define ST_ACCEL_1_BDU_MASK 0x80 #define ST_ACCEL_1_DRDY_IRQ_ADDR 0x22 #define ST_ACCEL_1_DRDY_IRQ_INT1_MASK 0x10 -#define ST_ACCEL_1_DRDY_IRQ_INT2_MASK 0x08 +#define ST_ACCEL_1_DRDY_IRQ_INT2_MASK 0x00 #define ST_ACCEL_1_MULTIREAD_BIT true /* CUSTOM VALUES FOR SENSOR 2 */