From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AG47ELuqS0pvmrOU50JYGt4YWlC4RbWF2Xrle32SiNzBGaNV7PKx1IVinXmRfE57wQMG4sjKuAad ARC-Seal: i=1; a=rsa-sha256; t=1520824119; cv=none; d=google.com; s=arc-20160816; b=gasFozg7OdDKe9I0+KB08PO9F1pRHO9wMjlBstO9V3bwa9ZVfR6mgG5Ma4lqHHfvnX 9tkc9H99iGVWyRn8/jID7baBmZmN0Lgvk+PXDkM+ImiVylpRBQj+/i29JqtWyRAF9OE3 XYut3wEYLA5Q0pQZZkz3ACEfiANDH0MN1GFluzhRVNTzVm6FNeh7ZuEC/eYHp/9Bfkj6 ZcxB8jbGSJ/QsDXkcIiA3F0d5kR2IimywjKqpmwSe8RuLC7H9X7Mp8KMI6SdvWuZN90j KqFoAAcaXJ8i7tCkPuLwtkD68HpNdsukYjRZw4NcKujMCpobyVLvynEd1bm0tOAW+mn5 X3tw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=in-reply-to:subject:message-id:date:cc:to:from:mime-version :content-transfer-encoding:content-disposition :arc-authentication-results; bh=U2A/LfTpvr1s9bXWTZ6MZH2kaZr7SBFWTQaT4NawRaU=; b=zdz6UYCEOrn/SsLa3CmG+9E7J8oWcddcLCxS4wkWdabRvO/toVU6nkQq2yF6S0fe5Q y/dj2dKRhvXOFkXv7++G3FzKJa4cdc8xGyOn4MUmbboAScaW8T/6RORFhD0d2O/V2dp7 gDro0KDN4UVMtecUE27yHjfVAuI6QmQkLF815ed7oezt0GR6dMgPQhIcnDvC1u6vA/Ok uHuLJetgd61qlhquICGVbZrfkKWz7sVE+hc+5k/uHeD3zp7I0rBtmlyDgiUoUEo/xf+z xRQ9oxN7AsDllAP02M+HEjmQ9pNAIK+mc1vps4XD/UrWkeAfk+kNvSoy0UOrmUoSVgDm FsNQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of ben@decadent.org.uk designates 88.96.1.126 as permitted sender) smtp.mailfrom=ben@decadent.org.uk Authentication-Results: mx.google.com; spf=pass (google.com: domain of ben@decadent.org.uk designates 88.96.1.126 as permitted sender) smtp.mailfrom=ben@decadent.org.uk Content-Type: text/plain; charset="UTF-8" Content-Disposition: inline Content-Transfer-Encoding: 8bit MIME-Version: 1.0 From: Ben Hutchings To: linux-kernel@vger.kernel.org, stable@vger.kernel.org CC: akpm@linux-foundation.org, "Ingo Molnar" , "Borislav Petkov" , "Thomas Gleixner" , "Dave Hansen" , "Eduardo Valentin" , "Juergen Gross" , "Peter Zijlstra" , "Denys Vlasenko" , "Josh Poimboeuf" , "David Laight" , "Rik van Riel" , "Brian Gerst" , keescook@google.com, "Dave Hansen" , "David Woodhouse" , "H. Peter Anvin" , "Will Deacon" , "Borislav Petkov" , daniel.gruss@iaik.tugraz.at, "Borislav Petkov" , "Linus Torvalds" , "Greg KH" , hughd@google.com, aliguori@amazon.com, "Boris Ostrovsky" , "Andy Lutomirski" Date: Mon, 12 Mar 2018 03:06:12 +0000 Message-ID: X-Mailer: LinuxStableQueue (scripts by bwh) Subject: [PATCH 3.16 04/76] x86/cpufeatures: Make CPU bugs sticky In-Reply-To: X-SA-Exim-Connect-IP: 2a02:8011:400e:2:6f00:88c8:c921:d332 X-SA-Exim-Mail-From: ben@decadent.org.uk X-SA-Exim-Scanned: No (on shadbolt.decadent.org.uk); SAEximRunCond expanded to false X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1594699671986206405?= X-GMAIL-MSGID: =?utf-8?q?1594699671986206405?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: 3.16.56-rc1 review patch. If anyone has any objections, please let me know. ------------------ From: Thomas Gleixner commit 6cbd2171e89b13377261d15e64384df60ecb530e upstream. There is currently no way to force CPU bug bits like CPU feature bits. That makes it impossible to set a bug bit once at boot and have it stick for all upcoming CPUs. Extend the force set/clear arrays to handle bug bits as well. Signed-off-by: Thomas Gleixner Reviewed-by: Borislav Petkov Cc: Andy Lutomirski Cc: Boris Ostrovsky Cc: Borislav Petkov Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: Dave Hansen Cc: David Laight Cc: Denys Vlasenko Cc: Eduardo Valentin Cc: Greg KH Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Juergen Gross Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Rik van Riel Cc: Will Deacon Cc: aliguori@amazon.com Cc: daniel.gruss@iaik.tugraz.at Cc: hughd@google.com Cc: keescook@google.com Link: https://lkml.kernel.org/r/20171204150606.992156574@linutronix.de Signed-off-by: Ingo Molnar Signed-off-by: David Woodhouse Signed-off-by: Greg Kroah-Hartman Signed-off-by: Ben Hutchings --- arch/x86/include/asm/cpufeature.h | 2 ++ arch/x86/include/asm/processor.h | 4 ++-- arch/x86/kernel/cpu/common.c | 6 +++--- 3 files changed, 7 insertions(+), 5 deletions(-) --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -286,6 +286,8 @@ extern const char * const x86_power_flag set_bit(bit, (unsigned long *)cpu_caps_set); \ } while (0) +#define setup_force_cpu_bug(bit) setup_force_cpu_cap(bit) + #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) #define cpu_has_vme boot_cpu_has(X86_FEATURE_VME) #define cpu_has_de boot_cpu_has(X86_FEATURE_DE) --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -147,8 +147,8 @@ extern struct cpuinfo_x86 boot_cpu_data; extern struct cpuinfo_x86 new_cpu_data; extern struct tss_struct doublefault_tss; -extern __u32 cpu_caps_cleared[NCAPINTS]; -extern __u32 cpu_caps_set[NCAPINTS]; +extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; +extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; #ifdef CONFIG_SMP DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -441,8 +441,8 @@ static const char *table_lookup_model(st return NULL; /* Not found */ } -__u32 cpu_caps_cleared[NCAPINTS]; -__u32 cpu_caps_set[NCAPINTS]; +__u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; +__u32 cpu_caps_set[NCAPINTS + NBUGINTS]; void load_percpu_segment(int cpu) { @@ -674,7 +674,7 @@ static void apply_forced_caps(struct cpu { int i; - for (i = 0; i < NCAPINTS; i++) { + for (i = 0; i < NCAPINTS + NBUGINTS; i++) { c->x86_capability[i] &= ~cpu_caps_cleared[i]; c->x86_capability[i] |= cpu_caps_set[i]; }