Re: pgprot_writecombine() and PATs on x86

[ebiederm@xmission.com (Eric W. Biederman)]

Roland Dreier <rdreier@cisco.com> writes:

>  > Roland is the mlx4 sane enough to put the memory that needs
>  > write-combining a prefetchable bar.  So several cards can be combined
>  > together?
>
> Yes, it is in a prefetchable BAR.  It's the second half of the second
> BAR in:
>
>     0d:00.0 InfiniBand: Mellanox Technologies Unknown device 634a (rev a0)
>             Subsystem: Mellanox Technologies Unknown device 634a
>             Flags: bus master, fast devsel, latency 0, IRQ 16
>             Memory at fc400000 (64-bit, non-prefetchable) [size=1M]
>             Memory at d8000000 (64-bit, prefetchable) [size=8M]
>             Memory at fc3fe000 (64-bit, non-prefetchable) [size=8K]
>             Capabilities: <access denied>
>
> but I'm not sure what you mean about combining several cards?

So in general the pci prefetchable attribute means write-combining as
well as prefetching is safe.  A sane BIOS will allocate prefetchable
BARS contiguously in the address space.  So on a good day you
can just use one MTRR to map all of the prefetchable BARs as write-combining.

Eric