From: adve@oce.nl (Arjan van de Ven)
To: jgarzik@mandrakesoft.com (Jeff Garzik)
Cc: linux-kernel@vger.kernel.org
Subject: Re: Error in x86 CPU capabilities starting with test5/6
Date: Fri, 17 Nov 2000 15:00:00 +0100 (CET) [thread overview]
Message-ID: <m13wm3c-000qDCC@pc1-adve.oce.nl> (raw)
In-Reply-To: <E13wkLK-0000bP-00@the-village.bc.nu> <qwwpujuvk1s.fsf@sap.com> <3A152DC1.21B35324@mandrakesoft.com> <qwwlmuivio0.fsf@sap.com> <20001117143150.A6832@gruyere.muc.suse.de> <3A15354B.4736A19@mandrakesoft.com>
In article <3A15354B.4736A19@mandrakesoft.com> you wrote:
> Andi Kleen wrote:
>> No it would not. Often you want cycle accurate couting for profiling
>> purposes.
> Isn't that why /dev/cpu/%d/msr exists?
This is root only though......
(Yes, you can crash AMD boxes by reading MSR's)
Greetings,
Arjan van de Ven
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next prev parent reply other threads:[~2000-11-17 14:32 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2000-11-17 9:50 Jordan
2000-11-17 11:39 ` Mikael Pettersson
2000-11-17 11:58 ` Tigran Aivazian
2000-11-17 12:10 ` Alan Cox
2000-11-17 12:51 ` Christoph Rohland
2000-11-17 13:08 ` Jeff Garzik
2000-11-17 13:21 ` Christoph Rohland
2000-11-17 13:31 ` Andi Kleen
2000-11-17 13:40 ` Jeff Garzik
2000-11-17 13:54 ` Andi Kleen
2000-11-17 14:02 ` Tigran Aivazian
2000-11-17 14:30 ` Christoph Rohland
2000-11-17 14:50 ` Alan Cox
2000-11-17 14:00 ` Arjan van de Ven [this message]
2000-11-17 15:18 ` Andrea Arcangeli
2000-11-17 16:06 ` Christoph Rohland
2000-11-17 18:28 ` Andrea Arcangeli
2000-11-18 9:57 ` Christoph Rohland
2000-11-19 10:31 ` Albert D. Cahalan
2000-11-17 13:38 ` Mikael Pettersson
2000-11-17 12:04 ` Andi Kleen
2000-11-17 12:14 ` Jan Niehusmann
2000-11-17 12:22 ` Andi Kleen
2000-11-17 13:26 ` Mohammad A. Haque
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