Re: [PATCH 2.6.21-rc5] MSI: read-flush MSI-X table

[ebiederm@xmission.com (Eric W. Biederman)]

Greg KH <greg@kroah.com> writes:

> On Mon, Mar 26, 2007 at 04:18:22PM -0700, Mitch Williams wrote:
>> This patch fixes a kernel bug which is triggered when using the
>> irqbalance daemon with MSI-X hardware.
>> 
>> Because both MSI-X interrupt messages and MSI-X table writes are posted,
>> it's possible for them to cross while in-flight.  This results in
>> interrupts being received long after the kernel thinks they're disabled,
>> and in interrupts being sent to stale vectors after rebalancing.
>> 
>> This patch performs a read flush after writes to the MSI-X table for
>> enable/disable and rebalancing operations.  Because this is an expensive
>> operation, we do not perform the read flush after mask/unmask
>> operations.  Hardware which supports MSI-X typically also supports some
>> sort of interrupt moderation, so a read-flush is not necessary for
>> mask/unmask operations.
>> 
>> This patch has been validated with (unreleased) network hardware which
>> uses MSI-X.
>
> How well does this play with the MSI core changes that Michael Ellerman
> has proposed on the linux-pci mailing list?

I guess I should add that I'm not certain that the code is exactly correct
there are weird differences between enable/disable and mask.  Where generally
the mask/unmask methods do the work and enable/disable do some weird software
thing.  Having them different and enable/disable not doing some software
thing concerns me a little.  I think mask/unmask may been overoptimized
in this case.

So I expect someone will wind up refactor this code at some point.

However the code is clearly better than what we have now, and it can't
affect anything else.

Eric