Re: [patch 23/26] x64, x2apic/intr-remap: MSI and MSI-X support for interrupt remapping infrastructure

[ebiederm@xmission.com (Eric W. Biederman)]

Suresh Siddha <suresh.b.siddha@intel.com> writes:

> On Fri, Jul 11, 2008 at 01:59:24AM -0700, Eric W. Biederman wrote:

> Sure. Will probably introduce irq_mapping_ops (which may be as simple as
> ops containing specific msi_compose_msg, ioapic_compose_rte, etc). This
> should simiplify the setup code. I will look into this and post these patches
> next week.

Thanks.  I am a little leery of separate hooks for different message
types.  As they are just different ways of encoding the information
for an interrupt message.  The index parameter seems to have placed
the same bits in the same relative location for both msi and the
ioapic_rte.  Which suggests to me that we have an architecturally
defined correspondence between the bits.  If that is indeed the case
and if we can continue to do that we should be able to keep the
complexity of the arch code down with sharing code, and letting the
iommu be oblivious to what part of the architecture will be sending
interrupt messages.

Although looking at it.  In theory if not in practice there are 64 bits
in an ioapic_rte message and 36 bits in an msi message (as long as we 
maintain the architecturally standard window).  So we may actually
be able to encode more information in one message then in the other.

>> need multiple irq_chip structures (although it may be worth it if we
>> can detect we can optimize irq migration).
>
> Depending on the IOMMU/hardware, they may define different irq_chip's
> if they add/simplify functionality, or may  use existing irq_chip's.

There are a lot of variables, as long as end result is relatively clean
and maintainable.

Eric