From: Andi Kleen <ak@muc.de>
To: Mikael Pettersson <mikpe@csd.uu.se>
Cc: linux-kernel@vger.kernel.org
Subject: Re: [PATCH] x86 performance counters driver 3.0-pre2 for 2.5.44: [2/4] x86 support
Date: 24 Oct 2002 17:49:55 +0200 [thread overview]
Message-ID: <m3wuo7omzg.fsf@averell.firstfloor.org> (raw)
In-Reply-To: <200210241500.RAA03585@kim.it.uu.se>
Mikael Pettersson <mikpe@csd.uu.se> writes:
> +struct per_cpu_cache { /* roughly a subset of perfctr_cpu_state */
> + union {
> + unsigned int p5_cesr;
> + unsigned int id; /* cache owner id */
> + } k1;
> + struct {
> + /* NOTE: these caches have physical indices, not virtual */
> + unsigned int evntsel[18];
> + unsigned int escr[0x3E2-0x3A0];
> + unsigned int pebs_enable;
> + unsigned int pebs_matrix_vert;
> + } control;
> +} __attribute__((__aligned__(SMP_CACHE_BYTES)));
> +static struct per_cpu_cache per_cpu_cache[NR_CPUS] __cacheline_aligned;
This should use per cpu data (asm/percpu.h) to save memory.
-Andi
next prev parent reply other threads:[~2002-10-24 15:43 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2002-10-24 15:00 Mikael Pettersson
2002-10-24 15:49 ` Andi Kleen [this message]
2002-10-25 12:25 ` Mikael Pettersson
2002-10-25 12:40 ` Andi Kleen
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