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Thu, 10 Jul 2025 16:23:00 +0200 (CEST) From: Andreas Schwab To: =?utf-8?Q?Cl=C3=A9ment_L=C3=A9ger?= Cc: linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Shuah Khan , Alexandre Ghiti Subject: Re: [PATCH v4] selftests: riscv: add misaligned access testing In-Reply-To: <5db9ec69-d0e4-4113-a989-ac75d0f1e5dd@rivosinc.com> (=?utf-8?Q?=22Cl=C3=A9ment=09L=C3=A9ger=22's?= message of "Thu, 10 Jul 2025 16:10:03 +0200") References: <20250710133506.994476-1-cleger@rivosinc.com> <5db9ec69-d0e4-4113-a989-ac75d0f1e5dd@rivosinc.com> Date: Thu, 10 Jul 2025 16:23:00 +0200 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Spam-Level: X-Spamd-Result: default: False [-4.20 / 50.00]; BAYES_HAM(-3.00)[100.00%]; NEURAL_HAM_LONG(-1.00)[-1.000]; NEURAL_HAM_SHORT(-0.20)[-0.989]; MIME_GOOD(-0.10)[text/plain]; RCVD_NO_TLS_LAST(0.10)[]; MIME_TRACE(0.00)[0:+]; DKIM_SIGNED(0.00)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FUZZY_RATELIMITED(0.00)[rspamd.com]; ARC_NA(0.00)[]; FROM_HAS_DN(0.00)[]; RCVD_COUNT_ONE(0.00)[1]; FROM_EQ_ENVFROM(0.00)[]; TO_DN_SOME(0.00)[]; MID_RHS_MATCH_FROM(0.00)[]; RCPT_COUNT_SEVEN(0.00)[8]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.de:email,suse.de:mid] X-Spam-Flag: NO X-Spam-Score: -4.20 On Jul 10 2025, Clément Léger wrote: > On 10/07/2025 15:53, Andreas Schwab wrote: >> On Jul 10 2025, Clément Léger wrote: >> >>> This selftest tests all the currently emulated instructions (except for >>> the RV32 compressed ones which are left as a future exercise for a RV32 >>> user). For the FPU instructions, all the FPU registers are tested. >> >> If that didn't catch the missing sign extension that I just fixed in >> , you >> should consider extending the tests. >> > > Hi Andreas, you link doesn't work and I didn't find anything about sign > extension except a patch you wrote for arch_cmpxg(). lore.k.o is currently down, here's the patch I have sent: >From 77c8255da24ee4fac54e2371594d7210d1ddee19 Mon Sep 17 00:00:00 2001 From: Andreas Schwab Date: Thu, 10 Jul 2025 13:52:35 +0200 Subject: [PATCH] riscv: traps_misaligned: properly sign extend value in misaligned load handler Add missing cast to signed long. Signed-off-by: Andreas Schwab --- arch/riscv/kernel/traps_misaligned.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index 93043924fe6c..f760e4fcc052 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -461,7 +461,7 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs) } if (!fp) - SET_RD(insn, regs, val.data_ulong << shift >> shift); + SET_RD(insn, regs, (long)(val.data_ulong << shift) >> shift); else if (len == 8) set_f64_rd(insn, regs, val.data_u64); else -- 2.50.0 -- Andreas Schwab, SUSE Labs, schwab@suse.de GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7 "And now for something completely different."