From: Andreas Schwab <schwab@suse.de>
To: Zhanpeng Zhang <zhangzhanpeng.jasper@bytedance.com>
Cc: Tomasz Jeznach <tjeznach@rivosinc.com>,
Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
iommu@lists.linux.dev, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, Xu Lu <luxu.kernel@bytedance.com>,
cuiyunhui@bytedance.com, yuanzhu@bytedance.com
Subject: Re: [PATCH v1] iommu/riscv: Support 32-bit register accesses
Date: Mon, 15 Jun 2026 10:21:12 +0200 [thread overview]
Message-ID: <mvmik7kz01z.fsf@suse.de> (raw)
In-Reply-To: <20260615064855.90316-1-zhangzhanpeng.jasper@bytedance.com> (Zhanpeng Zhang's message of "Mon, 15 Jun 2026 14:48:55 +0800")
On Jun 15 2026, Zhanpeng Zhang wrote:
> +config RISCV_IOMMU_32BIT_ACCESS
> + bool "Use 32-bit accesses for RISC-V IOMMU registers"
> + depends on RISCV_IOMMU
> + help
> + Say Y when the RISC-V IOMMU MMIO window cannot be accessed
> + using naturally aligned 64-bit loads and stores.
> +
> + When enabled, 64-bit IOMMU registers are accessed as paired
> + 32-bit MMIO operations. This option does not describe an RV32
> + kernel or a 32-bit IOMMU architecture.
What is the expected setting in a generic kernel?
--
Andreas Schwab, SUSE Labs, schwab@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."
next prev parent reply other threads:[~2026-06-15 8:21 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-15 6:48 Zhanpeng Zhang
2026-06-15 8:21 ` Andreas Schwab [this message]
2026-06-15 9:51 ` [External] " Zhanpeng Zhang
2026-06-15 9:59 ` David Laight
2026-06-15 13:21 ` [External] " Zhanpeng Zhang
2026-06-15 12:38 ` Guo Ren
2026-06-15 13:23 ` [External] " Zhanpeng Zhang
2026-06-16 10:36 ` David Laight
2026-06-16 15:47 ` Guo Ren
2026-06-16 19:51 ` David Laight
2026-06-17 16:24 ` Guo Ren
2026-06-17 21:54 ` David Laight
2026-06-18 3:36 ` Guo Ren
2026-06-18 3:20 ` Vivian Wang
2026-06-18 3:45 ` Guo Ren
2026-06-18 7:33 ` Vivian Wang
2026-06-18 9:51 ` Guo Ren
2026-06-18 10:01 ` Vivian Wang
2026-06-18 13:36 ` David Laight
2026-06-18 16:40 ` Guo Ren
2026-06-23 9:20 ` Zong Li
2026-06-28 8:20 ` Guo Ren
2026-06-29 1:15 ` Zong Li
2026-06-26 9:18 ` Zhanpeng Zhang
2026-07-13 6:09 ` [PATCH v2] iommu/riscv: Use 32-bit MMIO accesses for 64-bit registers Zhanpeng Zhang
2026-07-13 7:00 ` Guo Ren
2026-07-13 8:24 ` Zhanpeng Zhang
2026-07-13 12:29 ` [PATCH v3] " Zhanpeng Zhang
2026-07-14 2:02 ` Guo Ren
2026-07-14 7:10 ` Tomasz Jeznach
2026-07-14 12:27 ` Robin Murphy
2026-07-14 13:24 ` Guo Ren
2026-07-14 14:53 ` David Laight
2026-07-14 16:53 ` Guo Ren
2026-07-14 21:02 ` David Laight
2026-07-15 2:37 ` Guo Ren
2026-07-14 13:55 ` Guo Ren
2026-07-15 9:43 ` Chen Pei
2026-07-16 3:13 ` Zong Li
2026-07-16 4:04 ` Guo Ren
2026-07-16 6:59 ` Zong Li
2026-07-16 8:23 ` Guo Ren
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