Re: [PATCH v9 2/2] dmaengine: fsl-edma: Support dynamic scatter/gather chaining

["Benoît Monin" <benoit.monin@bootlin.com>]

On Friday, 11 September 2026 at 00:08:41 CEST, Frank Li wrote:
> > +      /* Link the SG descriptors with the available identifiers */
> > +      list_for_each_entry_safe(vdesc, tmp, &fsl_chan->vchan.desc_submitted, node) {
> > +              if (++issued_count > FIELD_MAX(EDMA_TCD_CSR_LINKCH))
> > +                      break;
> > +              fsl_edma_link_sg(fsl_chan, to_fsl_edma_desc(vdesc));
> > +              list_move_tail(&vdesc->node, &fsl_chan->vchan.desc_issued);
> 
> If this happen, it will depend on DONE irq to queue left desc_issued to
> hardware tcd? So there are idle gap?
> 
> I think it is fine, less possible longer than 31. I just want to confirm
> if my understand is correct.
> 
Yes, only 31 descriptors get linked at most, to make sure that we never get
the same link_sg_id twice in the issued queue. So we always know which
descriptor to handle in the end of transfer interrupt.

If we have more descriptors, their last TCD keep the D_REQ flag, and they
are handled one by one as we are doing today with a "stop-and-start" of the
channel.

[...]
> > +#define FSL_EDMA_DRV_EDMA3    (FSL_EDMA_DRV_SPLIT_REG |               \
> > +                               FSL_EDMA_DRV_BUS_8BYTE |               \
> > +                               FSL_EDMA_DRV_DEV_TO_DEV |              \
> > +                               FSL_EDMA_DRV_ALIGN_64BYTE |            \
> > +                               FSL_EDMA_DRV_CLEAR_DONE_E_SG |         \
> > +                               FSL_EDMA_DRV_CLEAR_DONE_E_LINK |       \
> > +                               FSL_EDMA_DRV_CSR_LINKCH)
> >
> > -#define FSL_EDMA_DRV_EDMA3    (FSL_EDMA_DRV_SPLIT_REG |       \
> > -                               FSL_EDMA_DRV_BUS_8BYTE |       \
> > -                               FSL_EDMA_DRV_DEV_TO_DEV |      \
> > -                               FSL_EDMA_DRV_ALIGN_64BYTE |    \
> > -                               FSL_EDMA_DRV_CLEAR_DONE_E_SG | \
> > -                               FSL_EDMA_DRV_CLEAR_DONE_E_LINK)
> > -
> > -#define FSL_EDMA_DRV_EDMA4    (FSL_EDMA_DRV_SPLIT_REG |       \
> > -                               FSL_EDMA_DRV_BUS_8BYTE |       \
> > -                               FSL_EDMA_DRV_DEV_TO_DEV |      \
> > -                               FSL_EDMA_DRV_ALIGN_64BYTE |    \
> > -                               FSL_EDMA_DRV_CLEAR_DONE_E_LINK)
> > +#define FSL_EDMA_DRV_EDMA4    (FSL_EDMA_DRV_SPLIT_REG |               \
> > +                               FSL_EDMA_DRV_BUS_8BYTE |               \
> > +                               FSL_EDMA_DRV_DEV_TO_DEV |              \
> > +                               FSL_EDMA_DRV_ALIGN_64BYTE |            \
> > +                               FSL_EDMA_DRV_CLEAR_DONE_E_LINK |       \
> > +                               FSL_EDMA_DRV_CSR_LINKCH)
> 
> Can you avoid move \ in this patch to reduce difference.
> 
Ok, I will revert that change and resend.

Best regards,
-- 
Benoît