Re: 2.6.0-test3-mm1: scheduling while atomic (ext3?)

[Andi Kleen <ak@suse.de>]

Alan Cox <alan@lxorguk.ukuu.org.uk> writes:

> On Mer, 2003-08-13 at 12:25, Andrew Morton wrote:
> > Like this?
> > 
> > What happens if someone runs a K6 kernel on a K7?
> > Or various other CPU types?  What is the matrix here?
> 
> Beats me, but then the prefetch code in 2.6 seems broken from
> 5 seconds of inspection anyway. We are testing the XMM feature
> and using prefetchnta for Athlon, thats wrong for lots of athlon
> processors that dont have XMM but do have prefetch/prefetchw,
> (which btw also seem to work properly on all these processors
>  while prefetchnta seems to do funky things)

The early Athlon Specific test was not done to avoid too much bloat.
(three alternatives instead of two)

Most Athlons in existence should have XMM already and the rest works.

You can hardly call that broken.

I would be surprised if prefetch behaves differently than prefetchnta
on Athlon. If the bug is similar to what happens on Opteron then
I bet it won't make a difference.

> For Athlon we should be testing 3Dnow, and using prefetch/prefetchw
> for Intel cases we want to go for prefetchnta if XMM is set (PIII, PIV)

That's done for write prefetches correctly.

(as Intel does not have a write prefetch)

-Andi