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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-39c84b97553sm25969171fa.33.2026.07.12.17.09.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Jul 2026 17:09:38 -0700 (PDT) Date: Mon, 13 Jul 2026 03:09:34 +0300 From: Dmitry Baryshkov To: Yongxing Mou Cc: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Abhinav Kumar Subject: Re: [PATCH RESEND v5 21/25] drm/msm/dpu: use msm_dp_get_mst_intf_id() to get the intf id Message-ID: References: <20260629-msm-dp-mst-v5-0-2ed6aee1867a@oss.qualcomm.com> <20260629-msm-dp-mst-v5-21-2ed6aee1867a@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260629-msm-dp-mst-v5-21-2ed6aee1867a@oss.qualcomm.com> X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzEyMDI2MSBTYWx0ZWRfXyTrck0cudXN8 ePKHXUbKeJyHGL7f4P69eK5O09cHyAPsOqi6xZtNl8CZ7snh18YVpWdWlb9w2vu6OgM9k0Xi+JE XXuRbjjcjWjYYJy2Dz33ggtSwcaL+VJWRUqK3QmqPmBm/mXQKuqcgOlhesmIanCyyDkfq3PAp5B YPfqVyTSZR1wxjl8vHwkmqFuXc/wVJ7b+/Lff8QtqJqIi7BBmZicfAgvzTVDrOu4zeHcncQWzUS 5Zc40bN/9XNMs/YLArk2iswOCBEBEV/xRpBJBC/JTA7oCBdSwtDQEubBAZ7cVToIxnwZyKr41JC bu+F+nXUxJfxHfSCp8SuMJ6mJiONjTZoFQ+xS4ycgmfqYtbOpHX4hnIyfdb2hweUJUtWJRbmqXF TOQe8/ygl8zkJQHxC9UCM21J3Fx4/aiHVy2lll5HBUieFNVJifX5px/GC7cnVVdyCjcAJLEurXM PdoUklRhkDw/72qFf7Q== X-Proofpoint-ORIG-GUID: 0M0nH_lEtlcgG_mxhJc5hCVSpduinael X-Proofpoint-Spam-Info: AW1haW4tMjYwNzEyMDI2MSBTYWx0ZWRfX3DeXZz6+Wg7W p+JaT8GWe0aFzpO7ssCCwYywQzq5YGIiPKKzQ5SHTPx3dxAjT2Va6pgo4I74n5Bhrzi/QcSdpe9 QbMni1ZauMkjSWrjVLVVn0DvWUbwaVs= X-Proofpoint-GUID: 0M0nH_lEtlcgG_mxhJc5hCVSpduinael X-Authority-Analysis: v=2.4 cv=aaJRWxot c=1 sm=1 tr=0 ts=6a542cc6 cx=c_pps a=wuOIiItHwq1biOnFUQQHKA==:117 a=xqWC_Br6kY4A:10 a=kj9zAlcOel0A:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=Ur00xY7Li4RbIHJ_WnoA:9 a=CjuIK1q_8ugA:10 a=XD7yVLdPMpWraOa8Un9W:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-12_08,2026-07-10_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 malwarescore=0 spamscore=0 suspectscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607120261 On Mon, Jun 29, 2026 at 10:14:42PM +0800, Yongxing Mou wrote: > Use msm_dp_get_mst_intf_id() to get the interface ID for the DP MST > controller as the intf_id is unique for each MST stream of each DP > controller. > > For DSI/eDP/DP SST, the stream_id is always 0, so existing behavior > remains unchanged. > > Signed-off-by: Abhinav Kumar > Signed-off-by: Yongxing Mou > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 20 +++++++++++--------- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2 ++ > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 4 ++++ > 3 files changed, 17 insertions(+), 9 deletions(-) This really should have been a part (or done before) the patch adding DPMST encoders. > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > index 1c74ff6f0dbd..3adfaeaab71d 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > @@ -1438,18 +1438,21 @@ void dpu_encoder_phys_disable(struct drm_encoder *drm_enc, > > static struct dpu_hw_intf *dpu_encoder_get_intf(const struct dpu_mdss_cfg *catalog, > struct dpu_rm *dpu_rm, > - enum dpu_intf_type type, u32 controller_id) > + struct msm_display_info *disp_info, u32 controller_id) As you are now passing whole msm_display_info, controller_id is available as disp_info->h_tile_instance[i]. Pass index to this function instead of passing controller_id. Ideally, split this patch into two: one changing the function to get disp_info, another one adding stream_id to the struct. > { > - int i = 0; > + int i = 0, cnt = 0; > + int stream_id = disp_info->stream_id; > > - if (type == INTF_WB) > + if (disp_info->intf_type == INTF_WB) > return NULL; > > + DPU_DEBUG("intf_type 0x%x controller_id %d stream_id %d\n", > + disp_info->intf_type, controller_id, stream_id); > for (i = 0; i < catalog->intf_count; i++) { > - if (catalog->intf[i].type == type > - && catalog->intf[i].controller_id == controller_id) { > - return dpu_rm_get_intf(dpu_rm, catalog->intf[i].id); > - } > + if (catalog->intf[i].type == disp_info->intf_type && > + controller_id == catalog->intf[i].controller_id) Why did you change the order of the args? > + if (cnt++ == stream_id) Squash into the condition. > + return dpu_rm_get_intf(dpu_rm, catalog->intf[i].id); > } > > return NULL; > @@ -2675,8 +2678,7 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, > i, controller_id, phys_params.split_role); > > phys_params.hw_intf = dpu_encoder_get_intf(dpu_kms->catalog, &dpu_kms->rm, > - disp_info->intf_type, > - controller_id); > + disp_info, controller_id); > > if (disp_info->intf_type == INTF_WB && controller_id < WB_MAX) > phys_params.hw_wb = dpu_rm_get_wb(&dpu_kms->rm, controller_id); > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h > index 25ade3dbbeda..861d69afbd76 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h > @@ -28,6 +28,7 @@ > * @h_tile_instance: Controller instance used per tile. Number of elements is > * based on num_of_h_tiles > * @is_cmd_mode Boolean to indicate if the CMD mode is requested > + * @stream_id stream id for which the interface needs to be acquired > * @vsync_source: Source of the TE signal for DSI CMD devices > */ > struct msm_display_info { > @@ -35,6 +36,7 @@ struct msm_display_info { > uint32_t num_of_h_tiles; > uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY]; > bool is_cmd_mode; > + int stream_id; > enum dpu_vsync_source vsync_source; > }; > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > index 91d33b432427..b32ecd5b0777 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > @@ -614,6 +614,7 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev, > info.h_tile_instance[info.num_of_h_tiles++] = other; > > info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->kms->dsi[i]); > + info.stream_id = 0; It is memset to 0. Drop this (here and below). > > rc = dpu_kms_dsi_set_te_source(&info, priv->kms->dsi[i]); > if (rc) { > @@ -689,6 +690,7 @@ static int _dpu_kms_initialize_displayport(struct drm_device *dev, > } > > for (stream_id = 0; stream_id < stream_cnt; stream_id++) { > + info.stream_id = stream_id; > encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DPMST, &info); > if (IS_ERR(encoder)) { > DPU_ERROR("encoder init failed for dp mst display\n"); > @@ -716,6 +718,7 @@ static int _dpu_kms_initialize_hdmi(struct drm_device *dev, > info.num_of_h_tiles = 1; > info.h_tile_instance[0] = 0; > info.intf_type = INTF_HDMI; > + info.stream_id = 0; > > encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_TMDS, &info); > if (IS_ERR(encoder)) { > @@ -748,6 +751,7 @@ static int _dpu_kms_initialize_writeback(struct drm_device *dev, > /* use only WB idx 2 instance for DPU */ > info.h_tile_instance[0] = wb_idx; > info.intf_type = INTF_WB; > + info.stream_id = 0; > > maxlinewidth = dpu_rm_get_wb(&dpu_kms->rm, info.h_tile_instance[0])->caps->maxlinewidth; > > > -- > 2.43.0 > -- With best wishes Dmitry