From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759372AbcJROKb (ORCPT ); Tue, 18 Oct 2016 10:10:31 -0400 Received: from mx2.suse.de ([195.135.220.15]:50524 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752710AbcJROKa (ORCPT ); Tue, 18 Oct 2016 10:10:30 -0400 Date: Tue, 18 Oct 2016 16:10:29 +0200 Message-ID: From: Takashi Iwai To: Mike Travis Cc: Ard Biesheuvel , , , Subject: Re: [PATCH] ALSA: hda - allow 40 bit DMA mask for NVidia devices In-Reply-To: References: <1476721439-29519-1-git-send-email-ard.biesheuvel@linaro.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI/1.14.6 (Maruoka) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 Emacs/24.5 (x86_64-suse-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI 1.14.6 - "Maruoka") Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 18 Oct 2016 14:46:29 +0200, Mike Travis wrote: > > > Have you tested this change on a system which has physical > addressing > 40 bits to insure that addresses > 40 bits are > not simply truncated to an incorrect (mod 40) address? > By not restricting the addresses to 32 bits you are not > restricting the device to the DMA32 zone. > > This is what caused the original panic on UV systems. But shouldn't it be handled properly by dma_set_mask() and dma_set_coherent_mask()? Takashi > Btw, the newest nVidia GPUs have > 40 bits of DMA address bits. > > On 10/18/2016 3:25 AM, Takashi Iwai wrote: > > On Mon, 17 Oct 2016 18:23:59 +0200, > > Ard Biesheuvel wrote: > >> > >> Commit 49d9e77e72cf ("ALSA: hda - Fix system panic when DMA > 40 bits > >> for Nvidia audio controllers") simply disabled any DMA exceeding 32 > >> bits for NVidia devices, even though they are capable of performing > >> DMA up to 40 bits. On some architectures (such as arm64), system memory > >> is not guaranteed to be 32-bit addressable by PCI devices, and so this > >> change prevents NVidia devices from working on platforms such as AMD > >> Seattle. > >> > >> Since the original commit already mentioned that up to 40 bits of DMA > >> is supported, and given that the code has been updated in the meantime > >> to support a 40 bit DMA mask on other devices, revert commit 49d9e77e72cf > >> and explicitly set the DMA mask to 40 bits for NVidia devices. > >> > >> Signed-off-by: Ard Biesheuvel > > > > Thanks, applied. Since this seems causing a real problem, I added Cc > > to stable. > > > > > > Takashi > > > > > >> --- > >> sound/pci/hda/hda_intel.c | 7 +++++-- > >> 1 file changed, 5 insertions(+), 2 deletions(-) > >> > >> diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c > >> index c3469f756ec2..c64d986009a9 100644 > >> --- a/sound/pci/hda/hda_intel.c > >> +++ b/sound/pci/hda/hda_intel.c > >> @@ -341,8 +341,7 @@ enum { > >> > >> /* quirks for Nvidia */ > >> #define AZX_DCAPS_PRESET_NVIDIA \ > >> - (AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \ > >> - AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\ > >> + (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\ > >> AZX_DCAPS_SNOOP_TYPE(NVIDIA)) > >> > >> #define AZX_DCAPS_PRESET_CTHDA \ > >> @@ -1716,6 +1715,10 @@ static int azx_first_init(struct azx *chip) > >> } > >> } > >> > >> + /* NVidia hardware normally only supports up to 40 bits of DMA */ > >> + if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA) > >> + dma_bits = 40; > >> + > >> /* disable 64bit DMA address on some devices */ > >> if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { > >> dev_dbg(card->dev, "Disabling 64bit DMA\n"); > >> -- > >> 2.7.4 > >> > >> >