From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752472AbdIRHDs (ORCPT ); Mon, 18 Sep 2017 03:03:48 -0400 Received: from smtpbgbr2.qq.com ([54.207.22.56]:43463 "EHLO smtpbgbr2.qq.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751648AbdIRHDr (ORCPT ); Mon, 18 Sep 2017 03:03:47 -0400 X-QQ-GoodBg: 0 X-QQ-SSF: 00100000000000F0 X-QQ-FEAT: 0YjEAxDCX1e7GJRqx5fkhuBaJIoxDcL/xos968aEHYXK8IDce4Yj4jfWnA6Bq VoLNALnXzl+IBFYmnxhyFCrBlseyR1YEzjpQyxYaqOV71jK7cV8fcYdw5IxDKb7aZfNct9z GtmgqaK1FVlFkVl3hyyEgmfb+/09jyFg0IcwM5NpLH5zuH6QYAZs2uv5dT/mAP9Rg8+dwpW uP2x9U6DgIoKpkoyMuDmX78fOuP/wUBJZGU/jNM99ebN0bswE6q2cyAI/INJg9JKKRayAh9 dyE2WIGjmgEnsasVu9/cj0wiJkIJWnNV5QKSYzR93Ws4Ze X-QQ-BUSINESS-ORIGIN: 2 X-Originating-IP: 222.92.124.153 X-QQ-STYLE: X-QQ-mid: bizmailfree34t1505718210t5288 From: "=?utf-8?B?6ZmI5Y2O5omN?=" To: "=?utf-8?B?Q2hyaXN0b3BoIEhlbGx3aWc=?=" Cc: "=?utf-8?B?SmFtZXMgRSAuIEogLiBCb3R0b21sZXk=?=" , "=?utf-8?B?TWFydGluIEsgLiBQZXRlcnNlbg==?=" , "=?utf-8?B?QW5kcmV3IE1vcnRvbg==?=" , "=?utf-8?B?RnV4aW4gWmhhbmc=?=" , "=?utf-8?B?bGludXgtc2NzaQ==?=" , "=?utf-8?B?bGludXgta2VybmVs?=" , "=?utf-8?B?c3RhYmxl?=" Subject: Re: [PATCH V5 3/3] scsi: Align queue to ARCH_DMA_MINALIGN innon-coherent DMA mode Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Date: Mon, 18 Sep 2017 15:03:30 +0800 X-Priority: 3 Message-ID: X-QQ-MIME: TCMime 1.0 by Tencent X-Mailer: QQMail 2.x X-QQ-Mailer: QQMail 2.x References: <1505708574-5281-1-git-send-email-chenhc@lemote.com> <20170918052051.GA29118@infradead.org> In-Reply-To: <20170918052051.GA29118@infradead.org> X-QQ-ReplyHash: 402870655 X-QQ-SENDSIZE: 520 Feedback-ID: bizmailfree:lemote.com:qybgforeign:qybgforeign2 X-QQ-Bgrelay: 1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by nfs id v8I73qdN004151 Hi, Christoph, I don't think dma_get_cache_alignment is the "absolute minimum alignment" in all cases. At least on MIPS/Loongson, if we use I/O coherent mode (Cached DMA mode), align block queue to 4Bytes is enough. If we align block queue to dma_get_cache_alignment in I/O coherent mode, there are peformance lost because we cannot use zero-copy in most cases (user buffers are usually not aligned). Huacai ------------------ Original ------------------ From: "Christoph Hellwig"; Date: Mon, Sep 18, 2017 01:20 PM To: "Huacai Chen"; Cc: "James E . J . Bottomley"; "Martin K . Petersen"; "Andrew Morton"; "Fuxin Zhang"; "linux-scsi"; "linux-kernel"; "stable"; Subject: Re: [PATCH V5 3/3] scsi: Align queue to ARCH_DMA_MINALIGN innon-coherent DMA mode Please send all patches in the series to the same to and cc lists. On Mon, Sep 18, 2017 at 12:22:54PM +0800, Huacai Chen wrote: > In non-coherent DMA mode, kernel uses cache flushing operations to > maintain I/O coherency, so scsi's block queue should be aligned to > ARCH_DMA_MINALIGN. Otherwise, it will cause data corruption, at least > on MIPS: > > Step 1, dma_map_single > Step 2, cache_invalidate (no writeback) > Step 3, dma_from_device > Step 4, dma_unmap_single > > If a DMA buffer and a kernel structure share a same cache line, and if > the kernel structure has dirty data, cache_invalidate (no writeback) > will cause data lost. And as said before we must _always_ align to dma_get_cache_alignment. This is even documented in Documentation/DMA-API.txt: ------------------------------ snip ------------------------------ int dma_get_cache_alignment(void) Returns the processor cache alignment. This is the absolute minimum alignment *and* width that you must observe when either mapping memory or doing partial flushes. ------------------------------ snip ------------------------------ > + if (device_is_coherent(dev)) > + blk_queue_dma_alignment(q, 0x04 - 1); > + else > + blk_queue_dma_alignment(q, dma_get_cache_alignment() - 1); So as said before this should become something like: blk_queue_dma_alignment(q, max(0x04, dma_get_cache_alignment()) - 1);