From: Yangyu Chen <cyy@cyyself.name>
To: linux-perf-users@vger.kernel.org, james.clark@linaro.org,
irogers@google.com, namhyung@kernel.org
Cc: acme@kernel.org, adrian.hunter@intel.com,
alexander.shishkin@linux.intel.com, fj3333bs@aa.jp.fujitsu.com,
fj5100bi@fujitsu.com, john.g.garry@oracle.com, jolsa@kernel.org,
kan.liang@linux.intel.com, leo.yan@linux.dev,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, mark.rutland@arm.com,
mike.leach@linaro.org, mingo@redhat.com, peterz@infradead.org,
will@kernel.org, Yangyu Chen <cyy@cyyself.name>
Subject: [PATCH] perf vendor events arm64: Fix incorrect CPU_CYCLE in metrics expr
Date: Thu, 13 Feb 2025 16:44:09 +0800 [thread overview]
Message-ID: <tencent_D4ED18476ADCE818E31084C60E3E72C14907@qq.com> (raw)
Some existing metrics for Neoverse N3 and V3 expressions use CPU_CYCLE
to represent the number of cycles, but this is incorrect. The correct
event to use is CPU_CYCLES.
I encountered this issue while working on a patch to add pmu events for
Cortex A720 and A520 by reusing the existing patch for Neoverse N3 and
V3 by James Clark [1] and my check script [2] reported this issue.
[1] https://lore.kernel.org/lkml/20250122163504.2061472-1-james.clark@linaro.org/
[2] https://github.com/cyyself/arm-pmu-check
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
---
.../perf/pmu-events/arch/arm64/arm/neoverse-n3/metrics.json | 6 +++---
.../perf/pmu-events/arch/arm64/arm/neoverse-v3/metrics.json | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/metrics.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/metrics.json
index 1f7c9536cb88..eb3a35f244e7 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/metrics.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/metrics.json
@@ -169,7 +169,7 @@
},
{
"MetricName": "fp_ops_per_cycle",
- "MetricExpr": "(FP_SCALE_OPS_SPEC + FP_FIXED_OPS_SPEC) / CPU_CYCLE",
+ "MetricExpr": "(FP_SCALE_OPS_SPEC + FP_FIXED_OPS_SPEC) / CPU_CYCLES",
"BriefDescription": "This metric measures floating point operations per cycle in any precision performed by any instruction. Operations are counted by computation and by vector lanes, fused computations such as multiply-add count as twice per vector lane for example.",
"MetricGroup": "FP_Arithmetic_Intensity",
"ScaleUnit": "1operations per cycle"
@@ -383,7 +383,7 @@
},
{
"MetricName": "nonsve_fp_ops_per_cycle",
- "MetricExpr": "FP_FIXED_OPS_SPEC / CPU_CYCLE",
+ "MetricExpr": "FP_FIXED_OPS_SPEC / CPU_CYCLES",
"BriefDescription": "This metric measures floating point operations per cycle in any precision performed by an instruction that is not an SVE instruction. Operations are counted by computation and by vector lanes, fused computations such as multiply-add count as twice per vector lane for example.",
"MetricGroup": "FP_Arithmetic_Intensity",
"ScaleUnit": "1operations per cycle"
@@ -421,7 +421,7 @@
},
{
"MetricName": "sve_fp_ops_per_cycle",
- "MetricExpr": "FP_SCALE_OPS_SPEC / CPU_CYCLE",
+ "MetricExpr": "FP_SCALE_OPS_SPEC / CPU_CYCLES",
"BriefDescription": "This metric measures floating point operations per cycle in any precision performed by SVE instructions. Operations are counted by computation and by vector lanes, fused computations such as multiply-add count as twice per vector lane for example.",
"MetricGroup": "FP_Arithmetic_Intensity",
"ScaleUnit": "1operations per cycle"
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/metrics.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/metrics.json
index d022ae25c864..4a671f55eaf3 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/metrics.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/metrics.json
@@ -169,7 +169,7 @@
},
{
"MetricName": "fp_ops_per_cycle",
- "MetricExpr": "(FP_SCALE_OPS_SPEC + FP_FIXED_OPS_SPEC) / CPU_CYCLE",
+ "MetricExpr": "(FP_SCALE_OPS_SPEC + FP_FIXED_OPS_SPEC) / CPU_CYCLES",
"BriefDescription": "This metric measures floating point operations per cycle in any precision performed by any instruction. Operations are counted by computation and by vector lanes, fused computations such as multiply-add count as twice per vector lane for example.",
"MetricGroup": "FP_Arithmetic_Intensity",
"ScaleUnit": "1operations per cycle"
@@ -383,7 +383,7 @@
},
{
"MetricName": "nonsve_fp_ops_per_cycle",
- "MetricExpr": "FP_FIXED_OPS_SPEC / CPU_CYCLE",
+ "MetricExpr": "FP_FIXED_OPS_SPEC / CPU_CYCLES",
"BriefDescription": "This metric measures floating point operations per cycle in any precision performed by an instruction that is not an SVE instruction. Operations are counted by computation and by vector lanes, fused computations such as multiply-add count as twice per vector lane for example.",
"MetricGroup": "FP_Arithmetic_Intensity",
"ScaleUnit": "1operations per cycle"
@@ -421,7 +421,7 @@
},
{
"MetricName": "sve_fp_ops_per_cycle",
- "MetricExpr": "FP_SCALE_OPS_SPEC / CPU_CYCLE",
+ "MetricExpr": "FP_SCALE_OPS_SPEC / CPU_CYCLES",
"BriefDescription": "This metric measures floating point operations per cycle in any precision performed by SVE instructions. Operations are counted by computation and by vector lanes, fused computations such as multiply-add count as twice per vector lane for example.",
"MetricGroup": "FP_Arithmetic_Intensity",
"ScaleUnit": "1operations per cycle"
--
2.47.2
next reply other threads:[~2025-02-13 8:51 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-13 8:44 Yangyu Chen [this message]
2025-02-13 10:52 ` James Clark
2025-02-20 18:26 ` Namhyung Kim
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