From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932841AbdHYUHn (ORCPT ); Fri, 25 Aug 2017 16:07:43 -0400 Received: from terminus.zytor.com ([65.50.211.136]:39617 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754518AbdHYUHk (ORCPT ); Fri, 25 Aug 2017 16:07:40 -0400 Date: Fri, 25 Aug 2017 13:04:00 -0700 From: tip-bot for Tony Luck Message-ID: Cc: linux-kernel@vger.kernel.org, ak@linux.intel.com, hpa@zytor.com, eranian@google.com, davidcc@google.com, vikas.shivappa@linux.intel.com, peterz@infradead.org, tglx@linutronix.de, tony.luck@intel.com, ravi.v.shankar@intel.com, fenghua.yu@intel.com, mingo@kernel.org Reply-To: eranian@google.com, davidcc@google.com, linux-kernel@vger.kernel.org, ak@linux.intel.com, hpa@zytor.com, fenghua.yu@intel.com, mingo@kernel.org, tony.luck@intel.com, ravi.v.shankar@intel.com, vikas.shivappa@linux.intel.com, peterz@infradead.org, tglx@linutronix.de In-Reply-To: References: To: linux-tip-commits@vger.kernel.org Subject: [tip:x86/cache] x86/intel_rdt: Move special case code for Haswell to a quirk function Git-Commit-ID: 0576113a387e0c8a5d9e24b4cd62605d1c9c0db8 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: 0576113a387e0c8a5d9e24b4cd62605d1c9c0db8 Gitweb: http://git.kernel.org/tip/0576113a387e0c8a5d9e24b4cd62605d1c9c0db8 Author: Tony Luck AuthorDate: Thu, 24 Aug 2017 09:26:50 -0700 Committer: Thomas Gleixner CommitDate: Fri, 25 Aug 2017 22:00:44 +0200 x86/intel_rdt: Move special case code for Haswell to a quirk function No functional change, but lay the ground work for other per-model quirks. Signed-off-by: Tony Luck Signed-off-by: Thomas Gleixner Cc: Fenghua" Cc: Ravi V" Cc: "Peter Zijlstra" Cc: "Stephane Eranian" Cc: "Andi Kleen" Cc: "David Carrillo-Cisneros" Cc: Vikas Shivappa Link: http://lkml.kernel.org/r/f195a83751b5f8b1d8a78bd3c1914300c8fa3142.1503512900.git.tony.luck@intel.com --- arch/x86/kernel/cpu/intel_rdt.c | 52 ++++++++++++++++++++++------------------- 1 file changed, 28 insertions(+), 24 deletions(-) diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c index 6935c8e..25514cd 100644 --- a/arch/x86/kernel/cpu/intel_rdt.c +++ b/arch/x86/kernel/cpu/intel_rdt.c @@ -172,34 +172,28 @@ static unsigned int cbm_idx(struct rdt_resource *r, unsigned int closid) * is always 20 on hsw server parts. The minimum cache bitmask length * allowed for HSW server is always 2 bits. Hardcode all of them. */ -static inline bool cache_alloc_hsw_probe(void) +static inline void cache_alloc_hsw_probe(void) { - if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && - boot_cpu_data.x86 == 6 && - boot_cpu_data.x86_model == INTEL_FAM6_HASWELL_X) { - struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3]; - u32 l, h, max_cbm = BIT_MASK(20) - 1; + struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3]; + u32 l, h, max_cbm = BIT_MASK(20) - 1; - if (wrmsr_safe(IA32_L3_CBM_BASE, max_cbm, 0)) - return false; - rdmsr(IA32_L3_CBM_BASE, l, h); - - /* If all the bits were set in MSR, return success */ - if (l != max_cbm) - return false; + if (wrmsr_safe(IA32_L3_CBM_BASE, max_cbm, 0)) + return; + rdmsr(IA32_L3_CBM_BASE, l, h); - r->num_closid = 4; - r->default_ctrl = max_cbm; - r->cache.cbm_len = 20; - r->cache.shareable_bits = 0xc0000; - r->cache.min_cbm_bits = 2; - r->alloc_capable = true; - r->alloc_enabled = true; + /* If all the bits were set in MSR, return success */ + if (l != max_cbm) + return; - return true; - } + r->num_closid = 4; + r->default_ctrl = max_cbm; + r->cache.cbm_len = 20; + r->cache.shareable_bits = 0xc0000; + r->cache.min_cbm_bits = 2; + r->alloc_capable = true; + r->alloc_enabled = true; - return false; + rdt_alloc_capable = true; } /* @@ -647,7 +641,7 @@ static __init bool get_rdt_alloc_resources(void) { bool ret = false; - if (cache_alloc_hsw_probe()) + if (rdt_alloc_capable) return true; if (!boot_cpu_has(X86_FEATURE_RDT_A)) @@ -689,8 +683,18 @@ static __init bool get_rdt_mon_resources(void) return !rdt_get_mon_l3_config(&rdt_resources_all[RDT_RESOURCE_L3]); } +static __init void rdt_quirks(void) +{ + switch (boot_cpu_data.x86_model) { + case INTEL_FAM6_HASWELL_X: + cache_alloc_hsw_probe(); + break; + } +} + static __init bool get_rdt_resources(void) { + rdt_quirks(); rdt_alloc_capable = get_rdt_alloc_resources(); rdt_mon_capable = get_rdt_mon_resources();